116 research outputs found
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Metamodeling-based Fast Optimization of Nanoscale Ams-socs
Modern consumer electronic systems are mostly based on analog and digital circuits and are designed as analog/mixed-signal systems on chip (AMS-SoCs). the integration of analog and digital circuits on the same die makes the system cost effective. in AMS-SoCs, analog and mixed-signal portions have not traditionally received much attention due to their complexity. As the fabrication technology advances, the simulation times for AMS-SoC circuits become more complex and take significant amounts of time. the time allocated for the circuit design and optimization creates a need to reduce the simulation time. the time constraints placed on designers are imposed by the ever-shortening time to market and non-recurrent cost of the chip. This dissertation proposes the use of a novel method, called metamodeling, and intelligent optimization algorithms to reduce the design time. Metamodel-based ultra-fast design flows are proposed and investigated. Metamodel creation is a one time process and relies on fast sampling through accurate parasitic-aware simulations. One of the targets of this dissertation is to minimize the sample size while retaining the accuracy of the model. in order to achieve this goal, different statistical sampling techniques are explored and applied to various AMS-SoC circuits. Also, different metamodel functions are explored for their accuracy and application to AMS-SoCs. Several different optimization algorithms are compared for global optimization accuracy and convergence. Three different AMS circuits, ring oscillator, inductor-capacitor voltage-controlled oscillator (LC-VCO) and phase locked loop (PLL) that are present in many AMS-SoC are used in this study for design flow application. Metamodels created in this dissertation provide accuracy with an error of less than 2% from the physical layout simulations. After optimal sampling investigation, metamodel functions and optimization algorithms are ranked in terms of speed and accuracy. Experimental results show that the proposed design flow provides roughly 5,000x speedup over conventional design flows. Thus, this dissertation greatly advances the state-of-the-art in mixed-signal design and will assist towards making consumer electronics cheaper and affordable
Analysis of design strategies for RF ESD problems in CMOS circuits
This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip
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Layout-accurate Ultra-fast System-level Design Exploration Through Verilog-ams
This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution
Development of electronics for microultrasound capsule endoscopy
Development of intracorporeal devices has surged in the last decade due to advancements in the semiconductor industry, energy storage and low-power sensing systems. This work aims to present a thorough systematic overview and exploration of the microultrasound (µUS) capsule endoscopy (CE) field as the development of electronic components will be key to a successful applicable µUSCE device. The research focused on investigating and designing high-voltage (HV, < 36 V) generating and driving circuits as well as a low-noise amplifier (LNA) for battery-powered and volume-limited systems.
In implantable applications, HV generation with maximum efficiency is required to improve the operational lifetime whilst reducing the cost of the device. A fully integrated hybrid (H) charge pump (CP) comprising a serial-parallel (SP) stage was designed and manufactured for > 20 V and 0 - 100 µA output capabilities. The results were compared to a Dickson (DKCP) occupying the same chip area; further improvements in the SPCP topology were explored and a new switching scheme for SPCPs was introduced. A second regulated CP version was excogitated and manufactured to use with an integrated µUS pulse generator. The CP was manufactured and tested at different output currents and capacitive loads; its operation with an US pulser was evaluated and a novel self-oscillating CP mechanism to eliminate the need of an auxiliary clock generator with a minimum area overhead was devised.
A single-output universal US pulser was designed, manufactured and tested with 1.5 MHz, 3 MHz, and 28 MHz arrays to achieve a means of fully-integrated, low-power transducer driving. The circuit was evaluated for power consumption and pulse generation capabilities with different loads. Pulse-echo measurements were carried out and compared with those from a commercial US research system to characterise and understand the quality of the generated pulse. A second pulser version for a 28 MHz array was derived to allow control of individual elements. The work involved its optimisation methodology and design of a novel HV feedback-based level-shifter.
A low-noise amplifier (LNA) was designed for a wide bandwidth µUS array with a centre frequency of 28 MHz. The LNA was based on an energy-efficient inverter architecture. The circuit encompassed a full power-down functionality and was investigated for a self-biased operation to achieve lower chip area. The explored concepts enable realisation of low power and high performance LNAs for µUS frequencies
A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries
Engineering andPhysical Science ResearchCouncil
(EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt
to improve standard cell libraries aimed at operation in the subthreshold regime and in
Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is
examined, with particular emphasis on how subthreshold physical effects degrade
robustness, variability and performance. How prevalent these physical effects are in a
commercial 65nm library is then investigated by extensive modeling of a BSIM4.5
compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out
and post-layout parasitically extracted models simulated to determine the
advantages/disadvantages of each. Full custom ring oscillators are designed and
manufactured. Measured results reveal a close correlation with the simulated results, with
frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices
respectively. The experiment provides the first silicon evidence of the improvement
capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well
as a mechanism of additional temperature stability in the subthreshold regime.
A novel sizing strategy is proposed and pursued to determine whether it is able to produce
a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit
AES cores are synthesized from the novel sizing strategy and compared against a third
AES core synthesized from a state-of-the-art subthreshold standard cell library used by
ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency
improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior
over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in
energy-per-cycle of 24% and frequency improvement of 8.65X.
A comparison to prior art is then performed. Valid cases are presented where the
proposed sizing strategy would be a candidate to produce superior subthreshold circuits
MOCAST 2021
The 10th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2021) will take place in Thessaloniki, Greece, from July 5th to July 7th, 2021. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue presents extended versions of top-ranking papers in the conference. The topics of MOCAST include:Analog/RF and mixed signal circuits;Digital circuits and systems design;Nonlinear circuits and systems;Device and circuit modeling;High-performance embedded systems;Systems and applications;Sensors and systems;Machine learning and AI applications;Communication; Network systems;Power management;Imagers, MEMS, medical, and displays;Radiation front ends (nuclear and space application);Education in circuits, systems, and communications
High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques
In this thesis, the applicability of Class-D amplifiers to integrated wide-band
communication line driver applications is studied. While Class-D techniques
can address some of the efficiency limitations of linear amplifier structures
and have shown promising results in low frequency applications, the low
frequency techniques and knowledge need further development in order to
improve their practicality for wide band systems.
New structures and techniques to extend the application of Class-D to
wide-band communication systems, in particular the HomePlug AV wire-
line communication standard, will be proposed. Additionally, the digital
processing requirements of these wide-band systems drives rapid movement
towards nanometer technology nodes and presents new challenges which will
be addressed, and new opportunities which will be exploited, for wide-band
integrated Class-D line drivers.
There are three main contributions of this research. First, a model of Class-D
efficiency degradation mechanisms is created, which allows the impact of
high-level design choices such as supply voltage, process technology and
operating frequency to be assessed. The outcome of this section is a strategy
for pushing the high efficiency of Class-D to wide band communication
applications, with switching frequencies up to many hundreds of Megahertz.
A second part of this research considers the design of efficient, fast and
high power Class-D output stages, as these are the major efficiency and
bandwidth bottleneck in wide-band applications. A novel NMOS-only totem
pole output stage with a fast, integrated drive structure will be proposed.
In a third section, a complete wide-band Class-D line driver is designed in a
0.13μm digital CMOS process. The line driver is systematically designed
using a rigorous development methodology and the aims are to maximise
the achievable signal bandwidth while minimising power dissipation. Novel
circuits and circuit structures are proposed as part of this section and the
resulting fabricated Class-D line driver test chip shows an efficiency of 15%
while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected
power
Advanced modelling and design considerations for interconnects in ultra- low power digital system
PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep
submicron (DSM) regime without decreasing chip area, the importance
of global interconnects increases but at the cost of
performance and power consumption for advanced System-on-
Chip (SoC)s. However, the growing complexity of interconnects
behaviour presents a challenge for their adequate modelling,
whereby conventional circuit theoretic approaches cannot provide
sufficient accuracy. During the last decades, fractional differential
calculus has been successfully applied to modelling
certain classes of dynamical systems while keeping complexity
of the models under acceptable bounds. For example, fractional
calculus can help capturing inherent physical effects in electrical
networks in a compact form, without following conventional
assumptions about linearization of non-linear interconnect components.
This thesis tackles the problem of interconnect modelling in
its generality to simulate a wide range of interconnection configurations,
its capacity to emulate irregular circuit elements
and its simplicity in the form of responsible approximation. This
includes modelling and analysing interconnections considering
their irregular components to add more flexibility and freedom
for design. The aim is to achieve the simplest adaptable model
with the highest possible accuracy. Thus, the proposed model
can be used for fast computer simulation of interconnection
behaviour. In addition, this thesis proposes a low power circuit
for driving a global interconnect at voltages close to the noise
level. As a result, the proposed circuit demonstrates a promising
solution to address the energy and performance issues related
to scaling effects on interconnects along with soft errors that
can be caused by neutron particles.
The major contributions of this thesis are twofold. Firstly, in
order to address Ultra-Low Power (ULP) design limitations, a novel
driver scheme has been configured. This scheme uses a bootstrap
circuitry which boosts the driver’s ability to drive a long
interconnect with an important feedback feature in it. Hence,
this approach achieves two objectives: improving performance
and mitigating power consumption. Those achievements are essential
in designing ULP circuits along with occupying a smaller
footprint and being immune to noise, observed in this design as
well. These have been verified by comparing the proposed design
to the previous and traditional circuits using a simulation tool.
Additionally, the boosting based approach has been shown beneficial
in mitigating the effects of single event upset (SEU)s, which
are known to affect DSM circuits working under low voltages.
Secondly, the CMOS circuit driving a distributed RLC load has
been brought in its analysis into the fractional order domain. This
model will make the on-chip interconnect structure easy to adjust
by including the effect of fractional orders on the interconnect
timing, which has not been considered before. A second-order
model for the transfer functions of the proposed general structure
is derived, keeping the complexity associated with second-order
models for this class of circuits at a minimum. The approach
here attaches an important trait of robustness to the circuit
design procedure; namely, by simply adjusting the fractional
order we can avoid modifying the circuit components. This can
also be used to optimise the estimation of the system’s delay
for a broad range of frequencies, particularly at the beginning
of the design flow, when computational speed is of paramount
importance.Iraqi Ministry of Higher Education
and Scientific Researc
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