Application of Taylor models to the worst-case analysis of stripline interconnects

This paper outlines a preliminary application of Taylor models to the worst-case analysis of transmission lines with bounded uncertain parameters. Taylor models are an algebraic technique that represents uncertain quantities in terms of a Taylor expansion complemented by an interval remainder encompassing approximation and truncation errors. The Taylor model formulation is propagated from input uncertainties to output responses through a suitable redef nition of the algebraic operations involved in their calculation. While the Taylor expansion def nes an analytical and parametric model of the response, the remainder provides a conservative bound inside which the true value is guaranteed to lie. The approach is validated against the SPICE simulation of a coupled stripline and shows promising accuracy and eff ciency

How affine arithmetic helps beat uncertainties in electrical systems

The ever-increasing impact of uncertainties in electronic circuits and systems is requiring the development of robust design tools capable of taking this inherent variability into account. Due to the computational inefficiency of repeated design trials, there has been a growing demand for smart simulation tools that can inherently and effectively capture the results of parameter variations on the system responses. To improve product performance, improve yield and reduce design cost, it is particularly relevant for the designer to be able to estimate worst-case responses. Within this framework, the article addresses the worst-case simulation of lumped and distributed electrical circuits. The application of interval-based methods, like interval analysis, Taylor models and affine arithmetic, is discussed and compared. The article reviews in particular the application of the affine arithmetic to complex algebra and fundamental matrix operations for the numerical frequency-domain simulation. A comprehensive and unambiguous discussion appears in fact to be missing in the available literature. The affine arithmetic turns out to be accurate and more efficient than traditional solutions based on Monte Carlo analysis. A selection of relevant examples, ranging from linear lumped circuits to distributed transmission-line structures, is used to illustrate this technique

Combined parametric and worst case circuit analysis via Taylor models

This paper proposes a novel paradigm to generate a parameterized model of the response of linear circuits with the inclusion of worst case bounds. The methodology leverages the so-called Taylor models and represents parameter-dependent responses in terms of a multivariate Taylor polynomial, in conjunction with an interval remainder accounting for the approximation error. The Taylor model representation is propagated from input parameters to circuit responses through a suitable redefinition of the basic operations, such as addition, multiplication or matrix inversion, that are involved in the circuit solution. Specifically, the remainder is propagated in a conservative way based on the theory of interval analysis. While the polynomial part provides an accurate, analytical and parametric representation of the response as a function of the selected design parameters, the complementary information on the remainder error yields a conservative, yet tight, estimation of the worst case bounds. Specific and novel solutions are proposed to implement complex-valued matrix operations and to overcome well-known issues in the state-of-the-art Taylor model theory, like the determination of the upper and lower bound of the multivariate polynomial part. The proposed framework is applied to the frequency-domain analysis of linear circuits. An in-depth discussion of the fundamental theory is complemented by a selection of relevant examples aimed at illustrating the technique and demonstrating its feasibility and strength

Fast high-order variation-aware IC interconnect analysis

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this thesis, three practical interconnect delay and slew analysis methods are presented to facilitate efficient evaluation of wire performance variability. The first method is described in detail in Chapter III. It harnesses a collection of computationally efficient procedures and closed-form formulas. By doing so, process variations are directly mapped into the variability of the output delay and slew. This method can provide the closed-form formulas of the output delay and slew at any sink node of the interconnect nets fully parameterized, in-process variations. The second method is based on adjoint sensitivity analysis and driving point model. It constructs the driving point model of the driver which drives the interconnect net by using the adjoint sensitivity analysis method. Then the driving point model can be propagated through the interconnect network by using the first method to obtain the closedform formulas of the output delay and slew. The third method is the generalized second-order adjoint sensitivity analysis. We give the mathematical derivation of this method in Chapter V. The theoretical value of this method is it can not only handle this particular variational interconnect delay and slew analysis, but it also provides an avenue for automatical linear network analysis and optimization. The proposed methods not only provide statistical performance evaluations of the interconnect network under analysis but also produce delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. Experimental results show that superior accuracy can be achieved by our proposed methods

Theoretical and practical aspects of linear and nonlinear model order reduction techniques

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 133-142).Model order reduction methods have proved to be an important technique for accelerating time-domain simulation in a variety of computer-aided design tools. In this study we present several new techniques for model reduction of the large-scale linear and nonlinear systems. First, we present a method for nonlinear system reduction based on a combination of the trajectory piecewise-linear (TPWL) method with truncated-balanced realizations (TBR). We analyze the stability characteristics of this combined method using perturbation theory. Second, we describe a linear reduction method that approximates TBR model reduction and takes advantage of sparsity of the system matrices or available accelerated solvers. This method is based on AISIAD (approximate implicit subspace iteration with alternate directions) and uses low-rank approximations of a system's gramians. This method is shown to be advantageous over the common approach of independently approximating the controllability and observability gramians, as such independent approximation methods can be inefficient when the gramians do not share a common dominant eigenspace. Third, we present a graph-based method for reduction of parameterized RC circuits. We prove that this method preserves stability and passivity of the models for nominal reduction. We present computational results for large collections of nominal and parameter-dependent circuits. Finally, we present a case study of model reduction applied to electroosmotic flow of a marker concentration pulse in a U-shaped microfluidic channel, where the marker flow in the channel is described by a three-dimensional convection-diffusion equation. First, we demonstrate the effectiveness of the modified AISIAD method in generating a low order models that correctly describe the dispersion of the marker in the linear case; that is, for the case of concentration-independent mobility and diffusion constants.(cont) Next, we describe several methods for nonlinear model reduction when the diffusion and mobility constants become concentration-dependent.by Dmitry Missiuro Vasilyev.Ph.D

ABSTRACT Interval-Valued Reduced Order Statistical Interconnect Modeling

We show how recent advances in the handling of correlated interval representations of range uncertainty can be used to predict the impact of statistical manufacturing variations on linear interconnect. We represent correlated statistical variations in RLC parameters as sets of correlated intervals, and show how classical model order reduction methods – AWE and PRIMA – can be re-targeted to compute interval-valued, rather than scalar-valued reductions. By applying a statistical interpretation and sampling to the resulting compact interval-valued model, we can efficiently estimate the impact of variations on the original circuit. Results show the technique can predict mean delay with errors between 5-10%, for correlated RLC parameter variations up to 35% 1

Crosstalk Noise Analysis for Nano-Meter VLSI Circuits.

Scaling of device dimensions into the nanometer process technology has led to a considerable reduction in the gate delays. However, interconnect delays have not scaled in proportion to gate delays, and global-interconnect delays account for a major portion of the total circuit delay. Also, due to process-technology scaling, the spacing between adjacent interconnect wires keeps shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. Hence, coupling noise has become an important issue which must be modeled while performing timing verification for VLSI chips. As delay noise strongly depends on the skew between aggressor-victim input transitions, it is not possible to a priori identify the victim-input transition that results in the worst-case delay noise. This thesis presents an analytical result that would obviate the need to search for the worst-case victim-input transition and simplify the aggressor-victim alignment problem significantly. We also propose a heuristic approach to compute the worst-case aggressor alignment that maximizes the victim receiver-output arrival time with current-source driver models. We develop algorithms to compute the set of top-k aggressors in the circuit, which could be fixed to reduce the delay noise of the circuit. Process variations cause variability in the aggressor-victim alignment which leads to variability in the delay noise. This variability is modeled by deriving closed-form expressions of the mean, the standard deviation and the correlations of the delay-noise distribution. We also propose an approach to estimate the confidence bounds on the path delay-noise distribution. Finally, we show that the interconnect corners obtained without incorporating the effects of coupling noise could lead to significant errors, and propose an approach to compute the interconnect corners considering the impact of coupling noise.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64663/1/gravkis_1.pd