Intelligent redundant actuation system requirements and preliminary system design

Several redundant actuation system configurations were designed and demonstrated to satisfy the stringent operational requirements of advanced flight control systems. However, this has been accomplished largely through brute force hardware redundancy, resulting in significantly increased computational requirements on the flight control computers which perform the failure analysis and reconfiguration management. Modern technology now provides powerful, low-cost microprocessors which are effective in performing failure isolation and configuration management at the local actuator level. One such concept, called an Intelligent Redundant Actuation System (IRAS), significantly reduces the flight control computer requirements and performs the local tasks more comprehensively than previously feasible. The requirements and preliminary design of an experimental laboratory system capable of demonstrating the concept and sufficiently flexible to explore a variety of configurations are discussed

Design of components for a generic microprocessor architecture

The objective of this thesis was to develop a generic microprocessor design that can be adapted to many of the existing 16 bit microprocessors. Common features of various microprocessors were used to develop the design of many generic components which can then be used to design the required microprocessors instead of custom-designing each one of them separately. The components were designed using a CISC based micro-programmed design approach as that was more suitable in terms of design and verification time for generic implementation. The generic parts designed include the Register File for temporary data storage, the Effective Address Calculator that generates the effective address for the operand, the Barrel Shifter for fast multiply/divide operations and the Priority Encoder for determining the processor state

A Microprocessor-based multivariable interactive control system

This study outlines the various types of control systems and reviews the necessary mathematical techniques to solve the problem of multivariable interactive control. The characteristics as well as the state representation for control processes involving either p or v type canonical structures are discussed. Next, the characteristics of multivariable interactive discrete control systems are discussed in detail. The advantages of flexibility and speed of microprocessors are used as powerful tools to implement a microprocessor-based system can be employed to control discrete processes. To demonstrate a practical application of a microprocessor-based system in a multivariable interactive discrete process, the algorithm and software (Assembly Language) is developed for a special engine control system selected as the model

A New Approach in Microprocessor/Microcontroller Courses/Laboratories Material Design and Development

Courses in microprocessors and microcontrollers are standard parts of the Engineering Technology core curricula. The traditional course material developments include both lectures and associated laboratory exercises. No matter how creative is the curriculum; it is usually budgetary constraints that confine the creativity when developing new curricula. This limits the freedom of the major approach in new course development. This article demonstrates new course lecture and laboratories material development that starts from ground up with both a hardware platform and simulation software design for microprocessor/microcontroller related courses. It is not only very cost effective, but also does not limit the instructor\u27s creativity when developing new curricula. The only obstacle is the instructor\u27s imagination on courses and laboratories activities. This system can be implemented at no cost to the department for sponsoring the courses. As a matter of fact, the initial trials of this system have generated revenue, thereby supporting future improvements and development needs. This new approach in course improvement starts with the design of a hardware platform in a custom made evaluation board. It involves the system circuit and power supply design, printed circuit board layout, prototype testing, and circuit board fabrication. The second step is to design the simulation software for laboratory uses. The total design and development of both software and hardware was a two year evolutionary process

Educational RTOS Development Board

The objective of this project was to facilitate student learning of embedded systems design. At WPI, students in ECE3849 must combine hardware and software concepts to develop real-time embedded systems in labs, a process which often frustrates students. This project identified ways to engage students in embedded systems design by 1) identifying ECE3849’s educational objectives 2) designing a versatile peripheral board to support new labs, 3) synthesizing student feedback on their frustrations and 4) developing targeted documentation for students to help alleviate their frustrations in labs. My development board, documentation, and critical analysis of student feedback provide recommendations for instructors to help future offerings of ECE3849 challenge students to design embedded systems

Design and fabrication of general purpose 8085 card and develop various interfacing cards useful in education of electronics

Not availabl

The "MIND" Scalable PIM Architecture

MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture

Advanced flight control system study

A fly by wire flight control system architecture designed for high reliability includes spare sensor and computer elements to permit safe dispatch with failed elements, thereby reducing unscheduled maintenance. A methodology capable of demonstrating that the architecture does achieve the predicted performance characteristics consists of a hierarchy of activities ranging from analytical calculations of system reliability and formal methods of software verification to iron bird testing followed by flight evaluation. Interfacing this architecture to the Lockheed S-3A aircraft for flight test is discussed. This testbed vehicle can be expanded to support flight experiments in advanced aerodynamics, electromechanical actuators, secondary power systems, flight management, new displays, and air traffic control concepts

Preliminary Candidate Advanced Avionics System (PCAAS)

Specifications which define the system functional requirements, the subsystem and interface needs, and other requirements such as maintainability, modularity, and reliability are summarized. A design definition of all required avionics functions and a system risk analysis are presented