3,033 research outputs found
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
On Regularity and Integrated DFM Metrics
Transistor geometries are well into the nanometer regime, keeping with Moore's Law. With this scaling in geometry, problems not significant in the larger geometries have come to the fore. These problems, collectively termed variability, stem from second-order effects due to the small geometries themselves and engineering limitations in creating the small geometries. The engineering obstacles have a few solutions which are yet to be widely adopted due to cost limitations in deploying them. Addressing and mitigating variability due to second-order effects comes largely under the purview of device engineers and to a smaller extent, design practices. Passive layout measures that ease these manufacturing limitations by regularizing the different layout pitches have been explored in the past. However, the question of the best design practice to combat systematic variations is still open. In this work we explore considerations for the regular layout of the exclusive-OR gate, the half-adder and full-adder cells implemented with varying degrees of regularity. Tradeoffs like complete interconnect unidirectionality, and the inevitable introduction of vias are qualitatively analyzed and some factors affecting the analysis are presented. Finally, results from the Calibre Critical Feature Analysis (CFA) of the cells are used to evaluate the qualitative analysis
Recommended from our members
Cross-Layer Pathfinding for Off-Chip Interconnects
Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Using Proportional-Integral-Differential approach for Dynamic Traffic Prediction in Wireless Network-on-Chip
The massive integration of cores in multi-core system has enabled chip designer to design systems while meeting the power performance demands of the applications. Wireless interconnection has emerged as an energy efficient solution to the challenges of multi-hop communication over the wireline paths in conventional Networks-on-Chips (NoCs). However, to ensure the full benefits of this novel interconnect technology, design of simple, fair and efficient Medium Access Control (MAC) mechanism to grant access to the on-chip wireless communication channel is needed. Moreover, to adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs). To ensure an efficient utilization of the wireless medium in a Wireless NoC (WiNoC), in this work we present the design of prediction model that is used by two dynamic MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. Through system level simulations, we show that the traffic aware MAC mechanisms are more energy efficient as well as capable of sustaining higher data bandwidth in WiNoCs
Exploring Spin-transfer-torque devices and memristors for logic and memory applications
As scaling CMOS devices is approaching its physical limits, researchers have begun exploring newer devices and architectures to replace CMOS.
Due to their non-volatility and high density, Spin Transfer Torque (STT) devices are among the most prominent candidates for logic and memory applications. In this research, we first considered a new logic style called All Spin Logic (ASL). Despite its advantages, ASL consumes a large amount of static power; thus, several optimizations can be performed to address this issue. We developed a systematic methodology to perform the optimizations to ensure stable operation of ASL.
Second, we investigated reliable design of STT-MRAM bit-cells and addressed the conflicting read and write requirements, which results in overdesign of the bit-cells. Further, a Device/Circuit/Architecture co-design framework was developed to optimize the STT-MRAM devices by exploring the design space through jointly considering yield enhancement techniques at different levels of abstraction.
Recent advancements in the development of memristive devices have opened new opportunities for hardware implementation of non-Boolean computing. To this end, the suitability of memristive devices for swarm intelligence algorithms has enabled researchers to solve a maze in hardware. In this research, we utilized swarm intelligence of memristive networks to perform image edge detection. First, we proposed a hardware-friendly algorithm for image edge detection based on ant colony. Next, we designed the image edge detection algorithm using memristive networks
5nm ์ดํ 3D Transistors์ Self-Heating ๋ฐ ์ ์ดํน์ฑ๋ถ์ ์ฐ๊ตฌ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2021.8. ์ ํ์ฒ .In this thesis, Self-Heating Effect (SHE) is investigated using TCAD simulations in various Sub-10-nm node Field Effect Transistor (FET). As the node decreases, logic devices have evolved into 3D MOSFET structures from Fin-FET to Nanosheet-FET. In the case of 3D MOSFET, there are thermal reliability issues due to the following reasons: โ
ฐ) The power density of the channel is high, โ
ฑ) The channel structure surrounded by SiO2, โ
ฒ) The overall low thermal conductivity characteristics due to scaling down. Many papers introduce the analysis and prediction of temperature rise by SHE in the device, but there are no papers presenting the content of mitigation of temperature rise. Therefore, we have studied the methods of decreasing the maximum lattice temperature (TL,max) such as shallow trench isolation (STI) composition engineering in Fin-FET, thermal analysis according to DC/AC/duty cycle in nanowire-FET, and active region ( e.g., gate metal thickness, channel width, channel number etc..) optimization in nanosheet-FET. In addition, lifetime affected by hot carrier injection (HCI) / bias-temperature instability (BTI) is also analyzed according to various thermal relaxation methods presented.์ด ๋
ผ๋ฌธ์์๋ ๋ค์ํ Sub-10nm ๋
ธ๋ ์ ๊ณ ํจ๊ณผ ํธ๋์ง์คํฐ (FET)์์ TCAD ์๋ฎฌ๋ ์ด์
์ ์ฌ์ฉํ์ฌ ์์ฒด ๋ฐ์ด ํจ๊ณผ (SHE)๋ฅผ ์กฐ์ฌํฉ๋๋ค. ๋
ธ๋๊ฐ ๊ฐ์ํจ์ ๋ฐ๋ผ ๋
ผ๋ฆฌ ์ฅ์น๋ Fin-FET์์ Nanosheet-FET๋ก 3D MOSFET ๊ตฌ์กฐ๋ก ์งํํ์ต๋๋ค. 3D MOSFET์ ๊ฒฝ์ฐ โ
ฐ) ์ฑ๋์ ์ ๋ ฅ ๋ฐ๋๊ฐ ๋์, โ
ฑ) SiO2๋ก ๋๋ฌ์ธ์ธ ์ฑ๋ ๊ตฌ์กฐ, โ
ฒ) ์ถ์๋ก ์ธํด ์ ์ฒด์ ์ผ๋ก ๋ฎ์ ์ด์ ๋ ํน์ฑ ๋ฑ ๋ค์๊ณผ ๊ฐ์ ์ด์ ๋ก ์ด ์ ๋ขฐ์ฑ ๋ฌธ์ ๊ฐ ์์ต๋๋ค. ํํธ, ๋ง์ ๋
ผ๋ฌธ์ด device์์ SHE์ ์ํ ์จ๋ ์์น์ ๋ถ์ ๋ฐ ์์ธก์ ์๊ฐํ์ง๋ง ์จ๋ ์์น ์ํ์ ๋ด์ฉ์ ์ ์ํ๋ ๋
ผ๋ฌธ์ ๊ฑฐ์ ์์ต๋๋ค. ๋ฐ๋ผ์ Fin-FET์ STI (Shallow Trench Isolation) ๊ตฌ์ฑ ๊ณตํ, nanowire-FET์ DC / AC / ๋ํฐ ์ฌ์ดํด์ ๋ฐ๋ฅธ ์ด ๋ถ์, nanosheet-FET์์ ์์์ ์ค์์์ญ(์: ๊ฒ์ดํธ ๊ธ์ ๋๊ป, ์ฑ๋ ํญ, ์ฑ๋ ๋ฒํธ ๋ฑ)์ ์ต์ ํ๋ฅผ ํตํด์ ์ต๋ ๊ฒฉ์ ์จ๋ (TL,max)๋ฅผ ๋ฎ์ถ๋ ๋ฐฉ๋ฒ๋ฑ์ ์ฐ๊ตฌํ์ต๋๋ค. ๋ํ ๋ ๋์๊ฐ์ HCI (Hot Carrier Injection) / BTI (Bias-Temperature Instability)์ ์ํฅ์ ๋ฐ๋ ์๋ช
๋ ์ ์๋ ๋ค์ํ ์ด ์ํ ๋ฐฉ๋ฒ์ ๋ฐ๋ผ ๋ถ์ํ์ฌ ์์์ ์ ์์ ์์ด ์ด์ ํน์ฑ๊ณผ ์๋ช
์ ์ข๊ฒ ๋ง๋๋ ์งํ๋ฅผ ์ ์ํฉ๋๋ค .Chapter 1 Introduction 1
1.1. Development of Semconductor structure 1
1.2. Self-Heating Effect issues in semiconductor devices 3
Chapter 2 Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing Ioff in Various Sub-10-nm 3-D Transistor 7
2.1. Introduction 7
2.2. Device Structure and Simulation Condition 7
2.3. Results and Discussion 12
2.4. Summary 27
Chapter 3 Analysis of Self Heating Effect in DC/AC Mode in Multi-channel GAA-Field Effect Transistor 32
3.1. Introduction 32
3.2. Multi-Channel Nanowire FET and Back End Of Line 33
3.3. Work Flow and Calibration Process 35
3.4. More Detailed Thermal Simulation of Nanowire-FET 37
3.5. Performance Analysis by Number of Channels 38
3.6. DC Characteristic of SHE in Nanowire-FETs 40
3.7. AC Characteristics of SHE in Nanowire-FETs 43
3.8. Summary 51
Chapter 4 Self-Heating and Electrothermal Properties of Advanced Sub-5-nm node Nanoplate FET 56
4.1. Introduction 56
4.2. Device Structure and Simulation Condition 57
4.3. Thermal characteristics by channel number and width 62
4.4. Thermal characteristics by inter layer-metal thickness (TM) 64
4.5. Life Time Prediction 65
4.6. Summary 67
Chapter 5 Study on Self Heating Effect and life time in Vertical-channel Field Effect Transistor 72
5.1. Introduction 72
5.2. Device Structure and Simulation Condition 72
5.3. Temperature and RTH according to channel width(TW) 76
5.4. Thermal properties according to air spacers and air gap 77
5.5. Ion boosting according to Channel numbers 81
5.6. Temperature imbalance of multi-channel VFETs 82
5.7. Mitigation of the channel temperature imbalance 86
5.8. Life time depending on various analysis conditions 88
5.9. Summary 89
Chapter 6 Conclusions 93
Appendix A. A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models 95
A.1. Introduction 95
A.2. Overall Schematic of the RF MOSFET Model 97
A.3. Verification of the DC Characteristics of the RF MOSFET Model 98
A.4. Verification of the MOSFET Model with Measured Y-parameters 100
A.5. Verification of the MOSFET Model with Measured Noise Parameters 101
A.6. Thermal Noise Extraction and Modeling (TNOIMOD = 0) 103
A.7. Verification of the Enhanced Model with Noise Parameters 112
A.8. Holistic Model (TNOIMOD = 1) 114
A.9. Evaluation the validity of the model for drain bias 115
A.10. Conclusion 117
Abstract in Korean 122๋ฐ
- โฆ