2,812 research outputs found

    Simulated annealing based datapath synthesis

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    Access and metro network convergence for flexible end-to-end network design

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    This paper reports on the architectural, protocol, physical layer, and integrated testbed demonstrations carried out by the DISCUS FP7 consortium in the area of access - metro network convergence. Our architecture modeling results show the vast potential for cost and power savings that node consolidation can bring. The architecture, however, also recognizes the limits of long-reach transmission for low-latency 5G services and proposes ways to address such shortcomings in future projects. The testbed results, which have been conducted end-to-end, across access - metro and core, and have targeted all the layers of the network from the application down to the physical layer, show the practical feasibility of the concepts proposed in the project

    Address generator synthesis

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    Management and Service-aware Networking Architectures (MANA) for Future Internet Position Paper: System Functions, Capabilities and Requirements

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    Future Internet (FI) research and development threads have recently been gaining momentum all over the world and as such the international race to create a new generation Internet is in full swing: GENI, Asia Future Internet, Future Internet Forum Korea, European Union Future Internet Assembly (FIA). This is a position paper identifying the research orientation with a time horizon of 10 years, together with the key challenges for the capabilities in the Management and Service-aware Networking Architectures (MANA) part of the Future Internet (FI) allowing for parallel and federated Internet(s)

    Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems

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    We present Swallow, a scalable many-core architecture, with a current configuration of 480 x 32-bit processors. Swallow is an open-source architecture, designed from the ground up to deliver scalable increases in usable computational power to allow experimentation with many-core applications and the operating systems that support them. Scalability is enabled by the creation of a tile-able system with a low-latency interconnect, featuring an attractive communication-to-computation ratio and the use of a distributed memory configuration. We analyse the energy and computational and communication performances of Swallow. The system provides 240GIPS with each core consuming 71--193mW, dependent on workload. Power consumption per instruction is lower than almost all systems of comparable scale. We also show how the use of a distributed operating system (nOS) allows the easy creation of scalable software to exploit Swallow's potential. Finally, we show two use case studies: modelling neurons and the overlay of shared memory on a distributed memory system.Comment: An open source release of the Swallow system design and code will follow and references to these will be added at a later dat
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