Linking Mixed-Signal Design and Test: Generation and Evaluation of Specification-Based Tests

The work described in this thesis is aimed at the exploration of new methods\ud for the integration of design and test development procedures for mixedsignal\ud integrated circuits (IC's). Mixed-signal IC's are currently found in\ud many electronic systems, including telecommunications, audio and video\ud instruments, automotive parts, etc. The testing of these IC's presents\ud problems due to the complex nature of analog functionality and the nonautomated\ud analog design process. Automatic generation of test programs\ud for analog parts is a problem which is not yet fully solved. Once a test is\ud generated, formal methods to ensure the quality of developed tests do not\ud exist or have a large overhead. Systematic links between design and test\ud development processes of analog and mixed-signal circuits are required to\ud improve these points and to ensure high quality and low time-to-market\ud (TTM) for mixed-signal IC's

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Digital analog converter for the extraction of test signals from mixed integrated circuits

The construction of integrated circuits involves testing the correct operation of its internal blocks. For this, a common practice is the integration of functional blocks to stimulate the internal subsystems and extract the responses to those stimuli. In this article, the design and simulation of a circuit for the extraction of the response signals of the devices under test in analog and mixed-signal integrated circuits is presented. The extraction block is a 2-stage 5-bit segmented A/D converter, operating at a sampling frequency of 10 MHz, implemented in a 0.12 µm technological process, which can be powered with 1.5 Vdc. This proposal offers a reduction in the area consumed, by requiring fewer comparators than other similar solutions found in the literature

Methodology for testing high-performance data converters using low-accuracy instruments

There has been explosive growth in the consumer electronics market during the last decade. As the IC industry is shifting from PC-centric to consumer electronics-centric, digital technologies are no longer solving all the problems. Electronic devices integrating mixed-signal, RF and other non-purely digital functions are becoming new challenges to the industry. When digital testing has been studied for long time, testing of analog and mixed-signal circuits is still in its development stage. Existing solutions have two major problems. First, high-performance mixed-signal test equipments are expensive and it is difficult to integrate their functions on chip. Second, it is challenging to improve the test capability of existing methods to keep up with the fast-evolving performance of mixed-signal products demanded on the market. The International Technology Roadmap for Semiconductors identified mixed-signal testing as one of the most daunting system-on-a-chip challenges;My works have been focused on developing new strategies for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Different from conventional methods that require test instruments to have better performance than the device under test, our algorithms allow the use of medium and low-accuracy instruments in testing. Therefore, we can provide practical and accurate test solutions for high-performance data converters. Meanwhile, the test cost is dramatically reduced because of the low price of such test instruments. These algorithms have the potential for built-in self-test and can be generalized to other mixed-signal circuitries. When incorporated with self-calibration, these algorithms can enable new design techniques for mixed-signal integrated circuits. Following contents are covered in the dissertation:;(1) A general stimulus error identification and removal (SEIR) algorithm that can test high-resolution ADCs using two low-linearity signals with a constant offset in between; (2) A center-symmetric interleaving (CSI) strategy for generating test signals to be used with the SEIR algorithm; (3) An architecture-based test algorithm for high-performance pipelined or cyclic ADCs using a single nonlinear stimulus; (4) Using Kalman Filter to improve the efficiency of ADC testing; and (5) A testing algorithm for high-speed high-resolution DACs using low-resolution ADCs with dithering

Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP

International audienceIn this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics

High-freequency CMOS VLSI chip testability and on-chip interconnect modeling

As high-speed digital and radio-frequency mixed-signal integrated circuits become increasingly common in product designs in industry, it is important for VLSI designers to be familiar with the challenges of chip testing and the behavior of circuit elements, including on-chip interconnect, at high frequencies. Expensive, specialized test equipment and software simulation packages for high-frequency chip testing and design are not always accessible for student research. This thesis documents the setup and characterization of a best-possible environment for high-frequency chip testing and data acquisition using existing laboratory equipment and resources. Experimental methodologies and measurement results of on-chip interconnect signal integrity and delay, ring oscillator noise and timing jitter, and time-domain reflectometry (TDR) testing are presented. Methods of modeling on-chip interconnect at high frequencies using field solvers and equivalent circuits are discussed. Lastly, the designs of single-ended and differential ring oscillators, for use in future voltage-controlled oscillator (VCO) and phase-locked loop (PLL) test chip designs, are presented and analyzed

Design of a Process Independent Tool for the Creation of On-Chip Serial Test Interfaces

The push towards higher performing and more sensitive mixed signal circuitry has required the parallel development of increasingly more complex and sensitive test and calibration harnesses. Current off-chip methods of test and calibration may require higher pin counts or induce unwanted parasitic interference. In this thesis, the design of a process independent tool for the creation of on-chip serial test interfaces is presented. This tool is part of a complete on-chip calibration solution designed by the author and his group for use in mixed signal integrated circuits. The system accomplishes several goals reducing pin count, minimizing parasitic interference, and facilitating test automation for the calibration and test harnesses by moving the test harness onto the die of the mixed signal integrated circuit. The tool presented in this paper was designed with the goals of easing test harness implementation, facilitating multiple fabrication processes, and providing flexibility to the chip designer. A set of serial test interfaces generated by the tool was fabricated in a 0.5um CMOS process in order to verify the both tool and its output

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Explicit characterization of bandgap references

Stable and precision voltage references are an integral part of many analog and mixed-signal integrated circuits. Bandgap references have been widely used for precision on-chip voltage sources in both bipolar and CMOS processes. Conspicuously absent in the literature are explicit relationships between the output voltage and temperature of bandgap references. Temperature characteristics of bipolar junction transistors (BJT\u27s) are developed to explicitly characterize the I-V relationship of BJT\u27s. Based on this characterization, an explicit relationship for the output voltage of a popular bandgap reference structure is developed. Within the context of this explicit relationship, temperature stability properties of references are explored.;Also included in this work is the introduction of a new digital calibration algorithm for pipeline ADCs and an order-dependent layout strategy that inherently cancels high-order gradient effects. The digital calibration algorithm does not require perturbation of the signal path through the pipeline and requires only code density test data generated from applying a simple non-critical test signal at the input. This calibration algorithm can be used to calibrate a multitude of ADC architectures. As a practical example, this method is used to calibrate a sub-radix pipeline ADC with minimal digital circuit overhead. By incorporating this calibration algorithm as part of the design process, the design requirements of the analog part of an ADC can be relaxed. The n th order central-symmetrical layout method provides cancellation of all spatial gradients up to nth order by using 2n unit cells in each element for pair-wise element matching. This method is useful for the layout of matching critical devices in high-precision circuits