Volterra Filtering for ADC Error Correction

Dynamic non-linearity of analog-to-digital converters (ADC) contributes significantly to the distortion of digitized signals. This paper introduces a new effective method for compensation such a distortion based on application of Volterra filtering. Considering an a-priori error model of ADC allows finding an efficient inverse Volterra model for error correction. Efficiency of proposed method is demonstrated on experimental results

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Longitudinal Cavity Mode Referenced Spline Tuning for Widely Tunable MG-Y Branch Semiconductor Laser

This paper presents a novel method for wavelength-continuous tuning of a MG-Y-Branch Laser that possesses an intrinsic self-calibration capability. The method utilizes the measured characteristic output power pattern caused by the internal longitudinal cavity modes of the laser device to calibrate a set of cubical spline curves. The spline curves are then used to generate the tuning currents for the two reflector sections and the phase section of the laser from an intermediate tuning control parameter. A calibration function maps the desired laser wavelength to the intermediate tuning parameter, thus enabling continuous tuning with high accuracy

Design of a multi-channel high precision wearable temperature collection system based on negative temperature coefficient thermistor

Body temperature is often used to screen infectious diseases and monitor treatment. Through the method of measuring the resistance of constant voltage temperature measuring circuit, a wearable multi-point body temperature monitoring system is researched and designed to determine skin surface temperature. The STM32F103C8T6 chip is used as the core processor, and the negative temperature coefficient thermistor (NTC) as the temperature sensing component. ADS1256 chip is a temperature signal conditioner, Bluetooth module is a wireless transmission unit, and LABVIEW is used to design the host computer interface. The constant voltage bridge circuit composed of thermistor and resistor voltage divider to carry out the acquisition of 8 channels of temperature data, and the 24bits ultra-high-precision analog-to-digital conversion module is configured with differential inputs to amplify, filter and convert analog signals; the converted data is processed and calculated in the single-chip microcomputer; finally, the data is transmitted to the host computer via Bluetooth. The thermistor is linearly compensated using the fourth-order formulation of the Stein-hart formula. Reduce the impact of environmental interference and uneven body temperature distribution from software and hardware. The error during the temperature measurement of temperature sensor is analyzed. The experimental results showed that the resolution of measurement system reached 0. 01 , and the temperature measurement accuracy was up to ± 0. 02 . This design scheme has high stability and accuracy; and the circuit is simple in structure, small in size, and low power consumption which can be used in occasions requiring precise body temperature measurement

Measurements, Models, Systems and Design

531 s.