Instruction Set Architectures for Quantum Processing Units

Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows. We briefly describe several prominent quantum computational models, their associated quantum processing units (QPUs), and the adoption of these devices as accelerators within high-performance computing systems. Emphasizing the interface to the QPU, we analyze instruction set architectures based on reduced and complex instruction sets, i.e., RISC and CISC architectures. We clarify the role of conventional constraints on memory addressing and instruction widths within the quantum computing context. Finally, we examine existing quantum computing platforms, including the D-Wave 2000Q and IBM Quantum Experience, within the context of future ISA development and HPC needs.Comment: To be published in the proceedings in the International Super Computing Conference 2017 publicatio

NOVEL RESOURCE EFFICIENT CIRCUIT DESIGNS FOR REBOOTING COMPUTING

CMOS based computing is reaching its limits. To take computation beyond Moores law (the number of transistors and hence processing power on a chip doubles every 18 months to 3 years) requires research explorations in (i) new materials, devices, and processes, (ii) new architectures and algorithms, (iii) new paradigm of logic bit representation. The focus is on fundamental new ways to compute under the umbrella of rebooting computing such as spintronics, quantum computing, adiabatic and reversible computing. Therefore, this thesis highlights explicitly Quantum computing and Adiabatic logic, two new computing paradigms that come under the umbrella of rebooting computing. Quantum computing is investigated for its promising application in high-performance computing. The first contribution of this thesis is the design of two resource-efficient designs for quantum integer division. The first design is based on non-restoring division algorithm and the second one is based on restoring division algorithm. Both the designs are compared and shown to be superior to the existing work in terms of T-count and T-depth. The proliferation of IoT devices which work on low-power also has drawn interests to the rebooting computing. Hence, the second contribution of this thesis is proving that Adiabatic Logic is a promising candidate for implementation in IoT devices. The adiabatic logic family called Symmetric Pass Gate Adiabatic Logic (SPGAL) is implemented in PRESENT-80 lightweight algorithm. Adiabatic Logic is extended to emerging transistor devices

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization

Continuing the scaling of quantum computers hinges on building classical control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the control processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.Comment: 10 pages, 8 figure

Characterization and Benchmarking of Quantum Computers

Quantum computers are a promising technology expected to provide substantial speedups to important computational problems, but modern quantum devices are imperfect and prone to noise. In order to program and debug quantum computers as well as monitor progress towards more advanced devices, we must characterize their dynamics and benchmark their performance. Characterization methods vary in measured quantities and computational requirements, and their accuracy in describing arbitrary quantum devices in an arbitrary context is not guaranteed. The leading techniques for characterization are based on fine-grain physical models that are typically accurate but computationally expensive. This raises the question of how to extend characterization efficiently to larger scales. We present an empirical-based approach to direct characterization of quantum circuits that reconciles accuracy with scalability by using a reduced set of test circuits that target a chosen application and coarse-graining the noise modeling process to reduce the model complexity. We show that this method performs well in tests with Greenberger-Horne-Zeilinger-state preparation circuits and the Bernstein-Vazirani algorithm, though it does not describe all error present in the system. We benchmark this method with the leading methods of gate set tomography, cycle benchmarking, and Pauli channel noise reconstruction to characterize quantum circuits and we compare the accuracy of these methods in predicting quantum device behavior. We find that our method for empirical direct characterization offers competitive accuracy when compared with finer-grained techniques, while significantly reducing the resources required for characterization. By testing on quantum devices, we quantify the quantum and classical resources required for each characterization method and we monitor the decrease in accuracy as a function of circuit size. We find that these characterization methods can provide an accurate estimate of a quantum computer\u27s performance on a benchmark but the best-performing method varied by test. Our results indicate that these characterization methods perform well in describing the noise of a quantum computer but their performance depends on the size and the context of the application

Efficacy of hardware scheduling on current generation quantum computers

Quantum computing is a rapidly advancing field of computer science that is increasingly becoming more practical. With these devices becoming more realistic, frameworks are needed by which the hardware resources, both quantum and classical, of quantum computers can be utilized more efficiently. This research aims to fill gaps in the research examining the effectiveness of hardware scheduling on the current generation of quantum computers. A hardware scheduling strategy is implemented using the A* search algorithm for routing qubits to conform with hardware limitations, and this algorithm is tested against a wide variety of quantum programs and devices. The effectiveness of the scheduler is determined through analysis of metrics obtained from the scheduling process. This particular scheduler proved to be effective for most of the tested algorithms and efficient for some, making it useful for general purposes, though some potential sources of improvement could increase the number of algorithms it is efficient for