ANÁLISE E DESENVOLVIMENTO DO MECANISMO DE POTENCIAL DE INVESTIMENTO DA REDE TURÍSTICA EM UMA PANDEMIA

Transformation of the mechanism for increasing the investment potential of the territories of Russia in the context of the COVID-2019 pandemic repeatedly strengthens the importance of an active policy in the field of forming the concept of promoting territories in general and in particular in the interregional market of tourist services. In the current conditions of the pandemic, fundamentally new goals and objectives of regional policy create the basis for the search for new tools and technologies in the field of promoting territories in the interregional market of tourist services. At the heart of formation of the concept of promoting the territory in the market of tourist services lies the effective use of its tourist potential and formation of inter-organizational relations in the tourist-recreational network of the territory, which contributes to an increase in the attractiveness of a city, a region on the inter-regional market of tourist services. When forming the concept of promoting domestic regions in the interregional tourism services market, in addition to the consequences of the pandemic, it is necessary to take into account the current long-term trends: insufficient popularization of domestic territories in the tourism services market. The unsatisfactory quality of tourist services provided is confirmed by the contribution of tourism to the gross domestic product of the Russian Federation, which amounted to only 5.0% in 2019, with an average global value of this indicator of 10.2%.La transformación del mecanismo para aumentar el potencial de inversión de los territorios de Rusia en el contexto de la pandemia de COVID-2019 refuerza repetidamente la importancia de una política activa en el campo de la formación del concepto de promoción de territorios en general y en particular en el mercado interregional de servicios turísticos. En las condiciones actuales de la pandemia, metas y objetivos fundamentalmente nuevos de la política regional sientan las bases para la búsqueda de nuevas herramientas y tecnologías en el campo de la promoción de territorios en el mercado interregional de servicios turísticos. En el corazón de la formación del concepto de promoción del territorio en el mercado de servicios turísticos se encuentra el aprovechamiento efectivo de su potencial turístico y la formación de relaciones interorganizacionales en la red turístico-recreativa del territorio, que contribuya al aumento de la atractivo de una ciudad, una región en el mercado interregional de servicios turísticos. Al formar el concepto de promoción de las regiones nacionales en el mercado de servicios turísticos interregionales, además de las consecuencias de la pandemia, es necesario tener en cuenta las tendencias actuales a largo plazo: insuficiente popularización de los territorios nacionales en el mercado de servicios turísticos. La calidad insatisfactoria de los servicios turísticos prestados se confirma por la contribución del turismo al producto interno bruto de la Federación de Rusia, que ascendió a solo el 5,0 % en 2019, con un valor global promedio de este indicador del 10,2 %.A transformação do mecanismo de aumento do potencial de investimento dos territórios da Rússia no contexto da pandemia de COVID-2019 reforça repetidamente a importância de uma política ativa no campo da formação do conceito de promoção de territórios em geral e em particular no mercado inter-regional de serviços turísticos. Nas condições atuais da pandemia, fundamentalmente novas metas e objetivos da política regional criam as bases para a busca de novas ferramentas e tecnologias no campo da promoção de territórios no mercado inter-regional de serviços turísticos. No cerne da formação do conceito de promoção do território no mercado de serviços turísticos está a utilização efetiva do seu potencial turístico e a formação de relações interorganizacionais na rede turístico-recreativa do território, o que contribui para um aumento da atratividade de uma cidade, uma região no mercado inter-regional de serviços turísticos. Ao formar o conceito de promoção das regiões domésticas no mercado de serviços turísticos inter-regionais, além das consequências da pandemia, é necessário levar em conta as tendências atuais de longo prazo: popularização insuficiente dos territórios domésticos no mercado de serviços turísticos. A qualidade insatisfatória dos serviços turísticos prestados é confirmada pela contribuição do turismo para o produto interno bruto da Federação Russa, que ascendeu a apenas 5,0% em 2019, com um valor médio global deste indicador de 10,2%

ANÁLISE E DESENVOLVIMENTO DO MECANISMO DE POTENCIAL DE INVESTIMENTO DA REDE TURÍSTICA EM UMA PANDEMIA

Transformation of the mechanism for increasing the investment potential of the territories of Russia in the context of the COVID-2019 pandemic repeatedly strengthens the importance of an active policy in the field of forming the concept of promoting territories in general and in particular in the interregional market of tourist services. In the current conditions of the pandemic, fundamentally new goals and objectives of regional policy create the basis for the search for new tools and technologies in the field of promoting territories in the interregional market of tourist services. At the heart of formation of the concept of promoting the territory in the market of tourist services lies the effective use of its tourist potential and formation of inter-organizational relations in the tourist-recreational network of the territory, which contributes to an increase in the attractiveness of a city, a region on the inter-regional market of tourist services. When forming the concept of promoting domestic regions in the interregional tourism services market, in addition to the consequences of the pandemic, it is necessary to take into account the current long-term trends: insufficient popularization of domestic territories in the tourism services market. The unsatisfactory quality of tourist services provided is confirmed by the contribution of tourism to the gross domestic product of the Russian Federation, which amounted to only 5.0% in 2019, with an average global value of this indicator of 10.2%.La transformación del mecanismo para aumentar el potencial de inversión de los territorios de Rusia en el contexto de la pandemia de COVID-2019 refuerza repetidamente la importancia de una política activa en el campo de la formación del concepto de promoción de territorios en general y en particular en el mercado interregional de servicios turísticos. En las condiciones actuales de la pandemia, metas y objetivos fundamentalmente nuevos de la política regional sientan las bases para la búsqueda de nuevas herramientas y tecnologías en el campo de la promoción de territorios en el mercado interregional de servicios turísticos. En el corazón de la formación del concepto de promoción del territorio en el mercado de servicios turísticos se encuentra el aprovechamiento efectivo de su potencial turístico y la formación de relaciones interorganizacionales en la red turístico-recreativa del territorio, que contribuya al aumento de la atractivo de una ciudad, una región en el mercado interregional de servicios turísticos. Al formar el concepto de promoción de las regiones nacionales en el mercado de servicios turísticos interregionales, además de las consecuencias de la pandemia, es necesario tener en cuenta las tendencias actuales a largo plazo: insuficiente popularización de los territorios nacionales en el mercado de servicios turísticos. La calidad insatisfactoria de los servicios turísticos prestados se confirma por la contribución del turismo al producto interno bruto de la Federación de Rusia, que ascendió a solo el 5,0 % en 2019, con un valor global promedio de este indicador del 10,2 %.A transformação do mecanismo de aumento do potencial de investimento dos territórios da Rússia no contexto da pandemia de COVID-2019 reforça repetidamente a importância de uma política ativa no campo da formação do conceito de promoção de territórios em geral e em particular no mercado inter-regional de serviços turísticos. Nas condições atuais da pandemia, fundamentalmente novas metas e objetivos da política regional criam as bases para a busca de novas ferramentas e tecnologias no campo da promoção de territórios no mercado inter-regional de serviços turísticos. No cerne da formação do conceito de promoção do território no mercado de serviços turísticos está a utilização efetiva do seu potencial turístico e a formação de relações interorganizacionais na rede turístico-recreativa do território, o que contribui para um aumento da atratividade de uma cidade, uma região no mercado inter-regional de serviços turísticos. Ao formar o conceito de promoção das regiões domésticas no mercado de serviços turísticos inter-regionais, além das consequências da pandemia, é necessário levar em conta as tendências atuais de longo prazo: popularização insuficiente dos territórios domésticos no mercado de serviços turísticos. A qualidade insatisfatória dos serviços turísticos prestados é confirmada pela contribuição do turismo para o produto interno bruto da Federação Russa, que ascendeu a apenas 5,0% em 2019, com um valor médio global deste indicador de 10,2%

Factors Affecting Company Value: Theoretical Study on Public Textile and Garment Manufacturing Company in Indonesia (2014 – 2019)

This study aims to examine the theoretical relationship between share ownership, dividend policy, corporate governance, and company value, in the context of textile and garment manufacturing companies listed at Indonesia Stock Exchange 2014 -2019. The sample in this study is the public textile and garment companies that publish annual financial reports consistently from 2014 to 2019. The population of this research is ten textile and garment companies. The sampling technique used was purposive sampling with a total of 30 observations (5 companies x 6 years) The data source is secondary data obtained from the annual report between the 2014-2019 period on the Indonesia Stock Exchange. The data analysis used is the outer model, outer loading after changing the model, and path analysis, with the help of the Partial Least Square program. The results of this study indicated that share ownership has a positive and significant effect on company value, dividend policy has a positive and significant effect on company value, good corporate governance has a negative and significant effect on company value. Keywords: Share Ownership Structure, Dividend Policy, Good Corporate Governance, Company Valu

Incremental Component-based Construction and Verification using Invariants

International audienceA new method for incremental computation of invariants is proposed, for checking incrementally safety properties of component-based systems described as the composition of interacting components. It improves the method applied by the D-Finder tool based on the computation of global invariants of composite components as solutions of a set of boolean behavioral constraints. These are induced by interactions on transition relations of the composed components. The new method uses a formalization of the incremental construction process of a composite component from a set of atomic components. Following the construction process, it decomposes the computation of global invariants of composite components into the computation of invariants of their constituent components. This is achieved by application of results relating boolean behavioral constraints of constituent components to global boolean behavioral constraints. The new method has been implemented in the D-Finder tool. Experimental results show significant gains in performance by applying the incremental computation of invariants in deadlock checking, with respect to the global verification method

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2010

Table of Contents: Copyright -- Conference Organization -- Tutorials -- Dimensions in Program Synthesis / by Sumit Gulwani, Microsoft (p. 1) -- Verifying VIA Nano Microprocessor Components / by Warren Hunt, Centaur Technology (p. 3) -- Session 1. Invited Talk -- Embedded Systems Design - Scientific Challenges and Work Directions / by Joseph Sifakis, Verimag (p. 11) -- Session 2. Industrial Track - Case Studies -- Formal Verification of an ASIC Ethernet Switch Block / by B.A. Krishna and Anamaya Sullerey, Chelsio Communications; and Alok Jain, Cadence Design Systems (p. 13) -- Formal Verification of Arbiters using Property Strengthening and Underapproximations / by Gadiel Auerbach and Fady Copty, IBM Haifa; and Viresh Paruthi, IBM Systems & Technology Group (p. 21) -- SAT-Based Semiformal Verification of Hardware / by Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel, Intel (p. 25) -- DFT Logic Verification through Property Based Formal Methods - SOC to IP / by Lopamudra Sen, Amit Roy, Supriya Bhattacharjee, and Bijitendra Mittra, Interra Systems India; and Subir K. Roy, Texas Instruments India (p. 33) -- Session 3. Software Verification -- SLAM2: Static Driver Verification with Under 4% False Alarms / by Thomas Ball, Ella Bounimova, Rahul Kumar, and Vladimir Levin, Microsoft (p. 35) -- Precise Static Analysis of Untrusted Driver Binaries / by Johannes Kinder, Technische Universität Darmstadt; and Helmut Veith, Technische Universität Wien (p. 43) -- Verifying SystemC: A Software Model Checking Approach / by Alessandro Cimatti, Andrea Micheli, Iman Narasamdya, and Marco Roveri, FBK-irst (p. 51) -- Session 4. Decision Procedures -- Coping with Moore’s Law (and More): Supporting Arrays in State-of-the-Art Model Checkers / by Jason Baumgartner, Michael Case, and Hari Mony, IBM Systems & Technology Group (p. 61) -- CalCS: SMT Solving for Non-Linear Convex Constraints / by Pierluigi Nuzzo, Alberto Puggelli, Sanjit A. Seshia, and Alberto Sangiovanni-Vincentelli, University of California Berkeley (p. 71) -- Integrating ICP and LRA Solvers for Deciding Nonlinear Real Arithmetic Problems / by Sicun Gao, NEC Labs America and Carnegie Mellon University; Malay Ganai, NEC Labs America; Franjo Ivančić, NEC Labs America; Aarti Gupta, NEC Labs America; Sriram Sankaranarayanan, University of Colorado at Boulder; and Edmund M. Clarke, Carnegie Mellon University (p. 81) -- Session 5. Synthesis -- A Halting Algorithm to Determine the Existence of Decoder / by Sheng Yu Shen, Ying Qin, JianMin Zhang, and SiKun Li, National University of Defense Technology (p. 91) -- Synthesis for Regular Specifications over Unbounded Domains / by Jad Hamza, ENS Cachan; Barbara Jobstmann, CNRS/Verimag; and Viktor Kuncak, EPFL (p. 101) -- Automatic Inference of Memory Fences / by Michael Kuperstein, Technion; Martin Vechev, IBM Research; and Eran Yahav, IBM Research & Technion (p. 111) -- Session 6. Industrial Track -- Applying SMT in Symbolic Execution of Microcode / by Anders Franzén, FBK-irst and DISI-University of Trento; Alessandro Cimatti, FBK-irst; Alexander Nadel, Intel Israel; Roberto Sebastiani, DISI-University of Trento; and Jonathan Shalev, Intel Israel (p. 121) -- Automated Formal Verification of Processors Based on Architectural Models / by Ulrich Kühne, ENS Cachan; Sven Beyer, OneSpin Solutions; Jörg Bormann, Abstract RT Solutions; and John Barstow, Infineon Technologies (p. 129) -- Encoding Industrial Hardware Verification Problems into Effectively Propositional Logic / by Moshe Emmer and Zurab Khasidashvili, Intel Israel; Konstantin Korovin and Andrei Voronkov, University of Manchester (p. 137) -- Session 7. Hardware and Protocol Verification -- Combinatorial Techniques for Sequential Equivalence Checking / by Hamid Savoj and David Berthelot, Envis Corporation; Alan Mishchenko and Robert Brayton, University of California Berkeley (p. 145) -- Automatic Verification of Estimate Functions with Polynomials of Bounded Functions / by Jun Sawada, IBM Austin (p. 151) -- A Framework for Incremental Modelling and Verification of On-Chip Protocols / by Peter Böhm, Oxford University (p. 159) -- Modular Specification and Verification of Interprocess Communication / by Eyad Alkassar, Saarland University; Ernie Cohen and Mark Hillebrand, European Microsoft Innovation Center; and Hristo Pentchev, Saarland University (p. 167) -- Session 8. Invited Talk -- Large-Scale Application of Formal Verification from Fiction to Fact / by Viresh Paruthi, IBM Systems & Technology Group (p. 175) -- Session 9. Abstraction -- A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction / by Niklas Een and Alan Mishchenko, University of California Berkeley; and Nina Amla, Cadence Research Laboratory (p. 181) -- Predicate Abstraction with Adjustable-Block Encoding / by Dirk Beyer and M. Erkan Keremoglu, Simon Fraser University; and Philipp Wendler, University of Passau (p. 189) -- Modular Bug Detection with Inertial Refinement / by Nishant Sinha, NEC Research Labs (p. 199) -- Path Predicate Abstraction by Complete Interval Property Checking / by Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, and Wolfgang Kunz, University of Kaiserslautern (p. 207) -- Session 10. SAT and QBF -- Relieving Capacity Limits on FPGA-Based SAT-Solvers / by Leopold Haller, Oxford University; and Satnam Singh, Microsoft Research (p. 217) -- Boosting Minimal Unsatisfiable Core Extraction / by Alexander Nadel, Intel Israel (p. 221) -- Propelling SAT and SAT-Based BMC using Careset / by Malay K. Ganai, NEC Laboratories America (p. 231) -- Efficiently Solving Quantified Bit-Vector Formulas / by Christoph M. Wintersteiger, ETH Zurich; Youssef Hamadi, Microsoft Research; and Leonardo de Moura, Microsoft Research (p. 239) -- Session 11. Verification of Concurrent Systems -- Boosting Multi-Core Reachability Performance with Shared Hash Tables / by Alfons Laarman, Jaco van de Pol, Michael Weber, University of Twente (p. 247) -- Incremental Component-Based Construction and Verification using Invariants / by Saddek Bensalem and Marius Bozga, Verimag Laboratory; Axel Legay, INRIA/IRISA; Thanh-Hung Nguyen, Joseph Sifakis, and Rongjie Yan, Verimag Laboratory (p. 257) -- Verifying Shadow Page Table Algorithms / by Eyad Alkassar, Saarland University; Ernie Cohen and Mark Hillebrand, European Microsoft Innovation Center; Mikhail Kovalev and Wolfgang J. Paul, Saarland University (p. 267) -- Exhibition -- Impacting Verification Closure Using Formal Analysis / by Massimo Roselli (p. 271) -- Scalable and Precise Program Analysis at NEC / by Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivančić, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan (University of Colorado at Boulder), Nishant Sinha, and Chao Wang, NEC Laboratories America (p. 273) -- Achieving Earlier Verification Closure Using Advanced Formal Verification / by Michael Siegel, OneSpin Solutions (p. 275) -- PINCETTE - Validating Changes and Upgrades in Networked Software / by Hana Chockler, IBM Israel (p. 277) -- Author Index20-23 October, 2010 in Lugano, Switzerlandhttp://www.cs.utexas.edu/users/hunt/FMCAD/Computer Science

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2010

Table of Contents: Copyright -- Conference Organization -- Tutorials -- Dimensions in Program Synthesis / by Sumit Gulwani, Microsoft (p. 1) -- Verifying VIA Nano Microprocessor Components / by Warren Hunt, Centaur Technology (p. 3) -- Session 1. Invited Talk -- Embedded Systems Design - Scientific Challenges and Work Directions / by Joseph Sifakis, Verimag (p. 11) -- Session 2. Industrial Track - Case Studies -- Formal Verification of an ASIC Ethernet Switch Block / by B.A. Krishna and Anamaya Sullerey, Chelsio Communications; and Alok Jain, Cadence Design Systems (p. 13) -- Formal Verification of Arbiters using Property Strengthening and Underapproximations / by Gadiel Auerbach and Fady Copty, IBM Haifa; and Viresh Paruthi, IBM Systems & Technology Group (p. 21) -- SAT-Based Semiformal Verification of Hardware / by Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel, Intel (p. 25) -- DFT Logic Verification through Property Based Formal Methods - SOC to IP / by Lopamudra Sen, Amit Roy, Supriya Bhattacharjee, and Bijitendra Mittra, Interra Systems India; and Subir K. Roy, Texas Instruments India (p. 33) -- Session 3. Software Verification -- SLAM2: Static Driver Verification with Under 4% False Alarms / by Thomas Ball, Ella Bounimova, Rahul Kumar, and Vladimir Levin, Microsoft (p. 35) -- Precise Static Analysis of Untrusted Driver Binaries / by Johannes Kinder, Technische Universität Darmstadt; and Helmut Veith, Technische Universität Wien (p. 43) -- Verifying SystemC: A Software Model Checking Approach / by Alessandro Cimatti, Andrea Micheli, Iman Narasamdya, and Marco Roveri, FBK-irst (p. 51) -- Session 4. Decision Procedures -- Coping with Moore’s Law (and More): Supporting Arrays in State-of-the-Art Model Checkers / by Jason Baumgartner, Michael Case, and Hari Mony, IBM Systems & Technology Group (p. 61) -- CalCS: SMT Solving for Non-Linear Convex Constraints / by Pierluigi Nuzzo, Alberto Puggelli, Sanjit A. Seshia, and Alberto Sangiovanni-Vincentelli, University of California Berkeley (p. 71) -- Integrating ICP and LRA Solvers for Deciding Nonlinear Real Arithmetic Problems / by Sicun Gao, NEC Labs America and Carnegie Mellon University; Malay Ganai, NEC Labs America; Franjo Ivančić, NEC Labs America; Aarti Gupta, NEC Labs America; Sriram Sankaranarayanan, University of Colorado at Boulder; and Edmund M. Clarke, Carnegie Mellon University (p. 81) -- Session 5. Synthesis -- A Halting Algorithm to Determine the Existence of Decoder / by Sheng Yu Shen, Ying Qin, JianMin Zhang, and SiKun Li, National University of Defense Technology (p. 91) -- Synthesis for Regular Specifications over Unbounded Domains / by Jad Hamza, ENS Cachan; Barbara Jobstmann, CNRS/Verimag; and Viktor Kuncak, EPFL (p. 101) -- Automatic Inference of Memory Fences / by Michael Kuperstein, Technion; Martin Vechev, IBM Research; and Eran Yahav, IBM Research & Technion (p. 111) -- Session 6. Industrial Track -- Applying SMT in Symbolic Execution of Microcode / by Anders Franzén, FBK-irst and DISI-University of Trento; Alessandro Cimatti, FBK-irst; Alexander Nadel, Intel Israel; Roberto Sebastiani, DISI-University of Trento; and Jonathan Shalev, Intel Israel (p. 121) -- Automated Formal Verification of Processors Based on Architectural Models / by Ulrich Kühne, ENS Cachan; Sven Beyer, OneSpin Solutions; Jörg Bormann, Abstract RT Solutions; and John Barstow, Infineon Technologies (p. 129) -- Encoding Industrial Hardware Verification Problems into Effectively Propositional Logic / by Moshe Emmer and Zurab Khasidashvili, Intel Israel; Konstantin Korovin and Andrei Voronkov, University of Manchester (p. 137) -- Session 7. Hardware and Protocol Verification -- Combinatorial Techniques for Sequential Equivalence Checking / by Hamid Savoj and David Berthelot, Envis Corporation; Alan Mishchenko and Robert Brayton, University of California Berkeley (p. 145) -- Automatic Verification of Estimate Functions with Polynomials of Bounded Functions / by Jun Sawada, IBM Austin (p. 151) -- A Framework for Incremental Modelling and Verification of On-Chip Protocols / by Peter Böhm, Oxford University (p. 159) -- Modular Specification and Verification of Interprocess Communication / by Eyad Alkassar, Saarland University; Ernie Cohen and Mark Hillebrand, European Microsoft Innovation Center; and Hristo Pentchev, Saarland University (p. 167) -- Session 8. Invited Talk -- Large-Scale Application of Formal Verification from Fiction to Fact / by Viresh Paruthi, IBM Systems & Technology Group (p. 175) -- Session 9. Abstraction -- A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction / by Niklas Een and Alan Mishchenko, University of California Berkeley; and Nina Amla, Cadence Research Laboratory (p. 181) -- Predicate Abstraction with Adjustable-Block Encoding / by Dirk Beyer and M. Erkan Keremoglu, Simon Fraser University; and Philipp Wendler, University of Passau (p. 189) -- Modular Bug Detection with Inertial Refinement / by Nishant Sinha, NEC Research Labs (p. 199) -- Path Predicate Abstraction by Complete Interval Property Checking / by Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, and Wolfgang Kunz, University of Kaiserslautern (p. 207) -- Session 10. SAT and QBF -- Relieving Capacity Limits on FPGA-Based SAT-Solvers / by Leopold Haller, Oxford University; and Satnam Singh, Microsoft Research (p. 217) -- Boosting Minimal Unsatisfiable Core Extraction / by Alexander Nadel, Intel Israel (p. 221) -- Propelling SAT and SAT-Based BMC using Careset / by Malay K. Ganai, NEC Laboratories America (p. 231) -- Efficiently Solving Quantified Bit-Vector Formulas / by Christoph M. Wintersteiger, ETH Zurich; Youssef Hamadi, Microsoft Research; and Leonardo de Moura, Microsoft Research (p. 239) -- Session 11. Verification of Concurrent Systems -- Boosting Multi-Core Reachability Performance with Shared Hash Tables / by Alfons Laarman, Jaco van de Pol, Michael Weber, University of Twente (p. 247) -- Incremental Component-Based Construction and Verification using Invariants / by Saddek Bensalem and Marius Bozga, Verimag Laboratory; Axel Legay, INRIA/IRISA; Thanh-Hung Nguyen, Joseph Sifakis, and Rongjie Yan, Verimag Laboratory (p. 257) -- Verifying Shadow Page Table Algorithms / by Eyad Alkassar, Saarland University; Ernie Cohen and Mark Hillebrand, European Microsoft Innovation Center; Mikhail Kovalev and Wolfgang J. Paul, Saarland University (p. 267) -- Exhibition -- Impacting Verification Closure Using Formal Analysis / by Massimo Roselli (p. 271) -- Scalable and Precise Program Analysis at NEC / by Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivančić, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan (University of Colorado at Boulder), Nishant Sinha, and Chao Wang, NEC Laboratories America (p. 273) -- Achieving Earlier Verification Closure Using Advanced Formal Verification / by Michael Siegel, OneSpin Solutions (p. 275) -- PINCETTE - Validating Changes and Upgrades in Networked Software / by Hana Chockler, IBM Israel (p. 277) -- Author Index20-23 October, 2010 in Lugano, Switzerlandhttp://www.cs.utexas.edu/users/hunt/FMCAD/Computer Science