6,777 research outputs found

    High-level synthesis for reduction of WCET in real-time systems

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    Efficient and predictable high-speed storage access for real-time embedded systems

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    As the speed, size, reliability and power efficiency of non-volatile storage media increases, and the data demands of many application domains grow, operating systems are being put under escalating pressure to provide high-speed access to storage. Traditional models of storage access assume devices to be slow, expecting plenty of slack time in which to process data between requests being serviced, and that all significant variations in timing will be down to the storage device itself. Modern high-speed storage devices break this assumption, causing storage applications to become processor-bound, rather than I/O-bound, in an increasing number of situations. This is especially an issue in real-time embedded systems, where limited processing resources and strict timing and predictability requirements amplify any issues caused by the complexity of the software storage stack. This thesis explores the issues related to accessing high-speed storage from real-time embedded systems, providing a thorough analysis of storage operations based on metrics relevant to the area. From this analysis, a number of alternative storage architectures are proposed and explored, showing that a simpler, more direct path from applications to storage can have a positive impact on efficiency and predictability in such systems

    Correct and efficient accelerator programming

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    This report documents the program and the outcomes of Dagstuhl Seminar 13142 “Correct and Efficient Accelerator Programming”. The aim of this Dagstuhl seminar was to bring together researchers from various sub-disciplines of computer science to brainstorm and discuss the theoretical foundations, design and implementation of techniques and tools for correct and efficient accelerator programming

    AMD GPUs as an Alternative to NVIDIA for Supporting Real-Time Workloads

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    mFish Alpha Pilot: Building a Roadmap for Effective Mobile Technology to Sustain Fisheries and Improve Fisher Livelihoods.

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    In June 2014 at the Our Ocean Conference in Washington, DC, United States Secretary of State John Kerry announced the ambitious goal of ending overfishing by 2020. To support that goal, the Secretary's Office of Global Partnerships launched mFish, a public-private partnership to harness the power of mobile technology to improve fisher livelihoods and increase the sustainability of fisheries around the world. The US Department of State provided a grant to 50in10 to create a pilot of mFish that would allow for the identification of behaviors and incentives that might drive more fishers to adopt novel technology. In May 2015 50in10 and Future of Fish designed a pilot to evaluate how to improve adoption of a new mobile technology platform aimed at improving fisheries data capture and fisher livelihoods. Full report

    Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

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    This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined
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