Improved force-directed scheduling in high-throughput digital signal processing

This paper discusses improved force-directed scheduling and its application in the design of high-throughput DSP systems, such as real-time video VLSL circuits. We present a mathematical justification of the technique of force-directed scheduling, introduced by Paulin and Knight (1989), and we show how the algorithm can be used to find cost-effective time assignments and resource allocations, allowing trade-offs between processing units and memories. Furthermore, we present modifications that improve the effectiveness and the efficiency of the algorithm. The significance of the improvements is illustrated by an empirical performance analysis based on a number of problem instance

Power-constrained block-test list scheduling

A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency, having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing provision. Test scheduling examples are discussed, highlighting further research steps towards an efficient system-level test scheduling algorith

Contraintes mémoire et solution architecturale pour applications TDSI

- Les systèmes supportant des applications de traitement du signal et de l'image manipulent de plus en plus de données. Cela entraîne une utilisation intensive de la mémoire qui devient le point critique du système ; la mémoire limite les performances et représente une proportion importante de la consommation globale. Dans le cadre du projet RNRT ALIPTA nous développons l'outil de synthèse d'architecture GAUT en nous intéressant à la synthèse de la partie mémoire. Nous évaluerons l'impact de contraintes de mémorisation sur les architectures pour différentes applications en traitement du signal et de l'image

The complexity of multidimensional periodic scheduling

AbstractWe discuss the computational complexity of the multidimensional periodic scheduling problem. This problem originates from the assignment of periodic tasks to processing units over time and it is related to the design of high-performance video signal processors. We present a model of multidimensional periodic operations and introduce the multidimensional periodic scheduling problem. Next, we show that this problem and two related sub-problems are NP-hard. Further-more, we identify several special cases induced by practical situations, of which some are proven to be polynomially solvable

레지스터에서의 소프트 에러 최소화를 위한 코드 생성 기법

학위논문 (석사)-- 서울대학교 대학원 : 전기컴퓨터공학부, 2012. 8. 김태환.공정 기술이 발전하고, 임베디드 프로세서가 소음이 있는 환경에서 많이 사용됨에 따라, 소프트 에러가 중요한 설계 문제가 되고 있다. 메모리의 용량이 상대적으로 크기 때문에 메모리 구조만 보호해왔지만, 레지스터 파일에서 에러 발생률이 더 높은 것이 증명되었다. 왜냐하면 레지스터 파일은 자주 액세스되기 때문에, 소프트 에러가 시스템의 다른 부분에 빠르게 전파될 수 있기 때문이다. 보호 기술이 몇 가지 제안되었지만, 이러한 기술은 성능, 공간 또는 에너지의 다양한 간접비가 있다. 또한, 그 기술들은 모든 에러를 검색할 수 없고, 감지가 되더라도 가끔은 수정할 수 없다. 이 논문은 이전 기술의 한계를 극복하는 것이다. 시스템이 이러한 에러에 의해 영향을 받을 수 있는 시간을 최소화할 수 있는 컴파일러 기법을 제안했다. 액세스 패턴 및 레지스터 사이의 종속성을 사용한 레지스터 취약점 분석을 바탕으로, 명령어 스케줄 재조정의 기법을 제안한다.As the process technology advances and embedded processors are frequently used in noisy environments, mitigating soft errors is becoming an important design issue. While only memory structures were considered worth protecting, it has been proven that the majority of the faults come from errors in the register files. Since register files are accessed very frequently, soft errors can easily and quickly be propagated to other parts of the system. A number of protection techniques of soft errors in register files have been proposed, but these techniques come with various overheads in performance, area or energy. Furthermore, they cannot detect all errors and sometimes cannot correct them even when detected. This work is to overcome the limitation of the previous techniques. Precisely, we develop a compiler-directed technique that can minimize the duration during which the system might be impacted by these errors. Based on the registers vulnerability analysis using the access patterns and dependencies between registers, we propose a technique of soft error aware instruction rescheduling.Abstract i Contents ii List of Figures iv List of Tables v Chapter 1 Introduction 1 Chapter 2 Force Directed Scheduling 5 2.1 Compute Time Frame 5 2.2 Type Distribution and Distribution Graph 6 2.3 Self-Force 8 2.4 Successor-Predecessor Force 8 2.5 Total Force and scheduling 9 Chapter 3 Minimal-Error Force Directed Scheduling 11 3.1 Register Dependency 11 3.2 Self-Force calculation 13 3.3 Sp-Force 14 3.4 Total Force and scheduling 15 3.5 Pseudo code 15 Chapter 4 Experimental Result 17 Chapter 5 Conclusion 19 Bibliography 21 초록 23Maste

Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors

Scheduling is one of the most often addressed optimization problems in DSP compilation, behavioral synthesis, and system-level synthesis research. With the rapid pace of changes in modern DSP applications requirements and implementation technologies, however, new types of scheduling challenges arise. This paper is concerned with the problem of scheduling blocks of computations in order to optimize the efficiency of their execution on programmable embedded systems under a realistic timing model of their processors. We describe an effective scheme for scheduling the blocks of any computation on a given system architecture and with a specified algorithm implementing each block. We also present algorithmic techniques for performing optimal block scheduling simultaneously with optimal architecture and algorithm selection. Our techniques address the block scheduling problem for both single- and multiple-processor system platforms and for a variety of optimization objectives including throughput, cost, and power dissipation. We demonstrate the practical effectiveness of our techniques on numerous designs and synthetic examples.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44804/1/10617_2004_Article_239764.pd