Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Apollo experience report guidance and control systems: Primary guidance, navigation, and control system development

The primary guidance, navigation, and control systems for both the lunar module and the command module are described. Development of the Apollo primary guidance systems is traced from adaptation of the Polaris Mark II system through evolution from Block I to Block II configurations; the discussion includes design concepts used, test and qualification programs performed, and major problems encountered. The major subsystems (inertial, computer, and optical) are covered. Separate sections on the inertial components (gyroscopes and accelerometers) are presented because these components represent a major contribution to the success of the primary guidance, navigation, and control system

Interactive Visualization of the Largest Radioastronomy Cubes

3D visualization is an important data analysis and knowledge discovery tool, however, interactive visualization of large 3D astronomical datasets poses a challenge for many existing data visualization packages. We present a solution to interactively visualize larger-than-memory 3D astronomical data cubes by utilizing a heterogeneous cluster of CPUs and GPUs. The system partitions the data volume into smaller sub-volumes that are distributed over the rendering workstations. A GPU-based ray casting volume rendering is performed to generate images for each sub-volume, which are composited to generate the whole volume output, and returned to the user. Datasets including the HI Parkes All Sky Survey (HIPASS - 12 GB) southern sky and the Galactic All Sky Survey (GASS - 26 GB) data cubes were used to demonstrate our framework's performance. The framework can render the GASS data cube with a maximum render time < 0.3 second with 1024 x 1024 pixels output resolution using 3 rendering workstations and 8 GPUs. Our framework will scale to visualize larger datasets, even of Terabyte order, if proper hardware infrastructure is available.Comment: 15 pages, 12 figures, Accepted New Astronomy July 201

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

MONet: Heterogeneous Memory over Optical Network for Large-Scale Data Centre Resource Disaggregation

Memory over Optical Network (MONet) system is a disaggregated data center architecture where serial (HMC) / parallel (DDR4) memory resources can be accessed over optically switched interconnects within and between racks. An FPGA/ASIC-based custom hardware IP (ReMAT) supports heterogeneous memory pools, accommodates optical-to-electrical conversion for remote access, performs the required serial/parallel conversion and hosts the necessary local memory controller. Optically interconnected HMC-based (serial I/O type) memory card is accessed by a memory controller embedded in the compute card, simplifying the hardware near the memory modules. This substantially reduces overheads on latency, cost, power consumption and space. We characterize CPU-memory performance, by experimentally demonstrating the impact of distance, number of switching hops, transceivers, channel bonding and bit-rate per transceiver on bit-error rate, power consumption, additional latency, sustained remote memory bandwidth/throughput (using industry standard benchmark STREAMS) and cloud workload performance (such as operations per second, average added latency and retired instructions per second on memcached with YCSB cloud workloads). MONet pushes the CPU-memory operational limit from a few centimetres to 10s of metres, yet applications can experience as low as 10% performance penalty (at 36m) compared to a direct-attached equivalent. Using the proposed parallel topology, a system can support up to 100,000 disaggregated cards

SIRU development. Volume 1: System development

A complete description of the development and initial evaluation of the Strapdown Inertial Reference Unit (SIRU) system is reported. System development documents the system mechanization with the analytic formulation for fault detection and isolation processing structure; the hardware redundancy design and the individual modularity features; the computational structure and facilities; and the initial subsystem evaluation results

Voyager spacecraft system, phase IA, TASK B - Preliminary design. Spacecraft functional design, volume A, book 2

Functional descriptions of subsystems for 1971 Voyager flight spacecraf

A Hybrid Parallel Algorithm for the 3-D Method of Characteristics Solution of the Boltzmann Transport Equation on High Performance Compute Clusters.

The focus of this thesis is on the development of a highly scalable parallel algorithm for solving the 3-D method of characteristics (MOC) form of the Boltzmann neutron transport equation. The derivation of the 3-D MOC method is presented first, along with the details of the discretization techniques, that utilize the concept of modular ray tracing. The implementation of these equations is then described, and then the approach to parallelizing the algorithm is discussed. Results are shown for a range of benchmark problems typically solved by 3-D neutron transport codes. The algorithm is parallelized in space, angle, and by characteristic rays, which is specific to the MOC solution method. Once the parallel algorithm is established, a performance model for the particular implementation is derived. This model contains detailed expressions for the number of floating point operations and execution time as a function of the problem size and fundamental computer hardware properties, such as the time per flop and cache access latency. The procedure for determining the hardware coefficients required by the performance model is then presented and validated using experimental results. The performance model is shown to agree well with experiment for both types of execution, and the model is therefore used for subsequent analyses that explore the algorithm's sensitivities to the computer and network hardware characteristics. The model is also analyzed to assess the scaling of the algorithm for a quarter core PWR. The optimization of the convergence of the parallel 3-D MOC algorithm through the use of the coarse mesh finite difference (CMFD) method is then developed. The CMFD accelerated parallel 3-D MOC algorithm is then used to compute solutions to several numerical benchmarks, that show good agreement with the reference results. Finally, the research performed in this thesis and its conclusions are summarized, and areas of future research are suggested.PHDNuclear Engineering & Radiological SciencesUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/100072/1/bkochuna_1.pd

Voyager spacecraft system. Prelimiary design, volume A /book 3 of 4/ - Flight spacecraft preferred design - G and C, Pwr, Eng'g mech, prop

Voyager spacecraft subsystem level requirements in guidance and control, power, propulsion, and engineering mechanics including structures and packagin