The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Experimental analysis of computer system dependability

This paper reviews an area which has evolved over the past 15 years: experimental analysis of computer system dependability. Methodologies and advances are discussed for three basic approaches used in the area: simulated fault injection, physical fault injection, and measurement-based analysis. The three approaches are suited, respectively, to dependability evaluation in the three phases of a system's life: design phase, prototype phase, and operational phase. Before the discussion of these phases, several statistical techniques used in the area are introduced. For each phase, a classification of research methods or study topics is outlined, followed by discussion of these methods or topics as well as representative studies. The statistical techniques introduced include the estimation of parameters and confidence intervals, probability distribution characterization, and several multivariate analysis methods. Importance sampling, a statistical technique used to accelerate Monte Carlo simulation, is also introduced. The discussion of simulated fault injection covers electrical-level, logic-level, and function-level fault injection methods as well as representative simulation environments such as FOCUS and DEPEND. The discussion of physical fault injection covers hardware, software, and radiation fault injection methods as well as several software and hybrid tools including FIAT, FERARI, HYBRID, and FINE. The discussion of measurement-based analysis covers measurement and data processing techniques, basic error characterization, dependency analysis, Markov reward modeling, software-dependability, and fault diagnosis. The discussion involves several important issues studies in the area, including fault models, fast simulation techniques, workload/failure dependency, correlated failures, and software fault tolerance

Testability issues in superconductor electronics

An emerging technology for solutions in high-end applications in computing and telecommunication is superconductor electronics. A system-level study has been carried out to verify the feasibility of DfT in superconductor electronics. In this paper, we present how this can be realized to monitor so-called single-flux quantum pulses. As a part of our research, test structures have been developed to detect structural defects in this technology. We also show detailed test results of those structures. It proves that it is possible to detect possible random defects and provide defect statistics for the Niobium-based fabrication process

Development of real-time cellular impedance analysis system

The cell impedance analysis technique is a label-free, non-invasive method, which simplifies sample preparation and allows applications requiring unmodified cell retrieval. However, traditional impedance measurement methods suffer from various problems (speed, bandwidth, accuracy) for extracting the cellular impedance information. This thesis proposes an improved system for extracting precise cellular impedance in real-time, with a wide bandwidth and satisfactory accuracy. The system hardware consists of five main parts: a microelectrode array (MEA), a stimulation circuit, a sensing circuit, a multi-function card and a computer. The development of system hardware is explored. Accordingly, a novel bioimpedance measurement method coined digital auto balancing bridge method, which is improved from the traditional analogue auto balancing bridge circuitry, is realized for real-time cellular impedance measurement. Two different digital bridge balancing algorithms are proposed and realized, which are based on least mean squares (LMS) algorithm and fast block LMS (FBLMS) algorithm for single- and multi-frequency measurements respectively. Details on their implementation in FPGA are discussed. The test results prove that the LMS-based algorithm is suitable for accelerating the measurement speed in single-frequency situation, whilst the FBLMS-based algorithm has advantages in stable convergence in multi-frequency applications. A novel algorithm, called the All Phase Fast Fourier Transform (APFFT), is applied for post-processing of bioimpedance measurement results. Compared with the classical FFT algorithm, the APFFT significantly reduces spectral leakage caused by truncation error. Compared to the traditional FFT and Digital Quadrature Demodulation (DQD) methods, the APFFT shows excellent performance for extracting accurate phase and amplitude in the frequency spectrum. Additionally, testing and evaluation of the realized system has been performed. The results show that our system achieved a satisfactory accuracy within a wide bandwidth, a fast measurement speed and a good repeatability. Furthermore, our system is compared with a commercial impedance analyzer (Agilent 4294A) in biological experiments. The results reveal that our system achieved a comparable accuracy to the commercial instrument in the biological experiments. Finally, conclusions are given and the future work is proposed

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Implementation of verification methodologies

The increasing complexity of design elevates the importance of verification. This report explores different verification methodologies. The second chapter emphasizes the importance of testability and establishes the synthesis and DFT insertion flow using an SoC with ARM-Amber core as an example. Also, formal equivalence check is performed between the golden model, that is, RTL against its netlist. The third chapter delineates the design and formal verification of an Arbiter with APB slave configuration port. The design is extensively verified by writing SystemVerilog properties and we learn that the verification is only as good as the properties. Fourth chapter further explores formal verification with a different approach. The implemented x86 execution unit is formally verified by developing the its reference model and writing simple equality assertion checks. This approach exploits both, completeness of formal as well as includes the UVM reference model which reduces the long list of properties required for formal. The last chapter provides an approach to identify the critical registers in design. The critical flops in the design as a subset of all the registers which may have the most effect on the control flow of a module. This finds application in selecting the relevant auto-generated properties.Electrical and Computer Engineerin