Design techniques for low-power systems

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low-power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system including error control, system decomposition, communication and MAC protocols, and low-power short range networks

Parametric Macromodels of Differential Drivers and Receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link

Spin-Based Neuron Model with Domain Wall Magnets as Synapse

We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

Fast synchronization 3R burst-mode receivers for passive optical networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed

Low Power system Design techniques for mobile computers

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, sys tem decomposition, communication and MAC protocols, and low power short range net works

Fuzzy second order sliding mode control of a unified power flow controller

Purpose. This paper presents an advanced control scheme based on fuzzy logic and second order sliding mode of a unified power flow controller. This controller offers advantages in terms of static and dynamic operation of the power system such as the control law is synthesized using three types of controllers: proportional integral, and sliding mode controller and Fuzzy logic second order sliding mode controller. Their respective performances are compared in terms of reference tracking, sensitivity to perturbations and robustness. We have to study the problem of controlling power in electric system by UPFC. The simulation results show the effectiveness of the proposed method especiallyin chattering-free behavior, response to sudden load variations and robustness. All the simulations for the above work have been carried out using MATLAB / Simulink. Various simulations have given very satisfactory results and we have successfully improved the real and reactive power flows on a transmission lineas well as to regulate voltage at the bus where it is connected, the studies and illustrate the effectiveness and capability of UPFC in improving power.В настоящей статье представлена усовершенствованная схема управления, основанная на нечеткой логике и режиме скольжения второго порядка унифицированного контроллера потока мощности. Данный контроллер обладает преимуществами с точки зрения статической и динамической работы энергосистемы, например, закон управления синтезируется с использованием трех типов контроллеров: пропорционально-интегрального, контроллера скользящего режима и контроллера скользящего режима нечеткой логики второго порядка. Их соответствующие характеристики сравниваются с точки зрения отслеживания эталонов, чувствительности к возмущениям и надежности. Необходимо изучить проблему управления мощностью в энергосистеме с помощью унифицированного контроллера потока мощности (UPFC). Результаты моделирования показывают эффективность предложенного метода, особенно в отношении отсутствия вибрации, реакции на внезапные изменения нагрузки и устойчивости. Все расчеты для вышеуказанной работы были выполнены с использованием MATLAB/Simulink. Различные расчетные исследования дали весьма удовлетворительные результаты, и мы успешно улучшили потоки реальной и реактивной мощности на линии электропередачи, а также регулирование напряжения на шине, к которой она подключена, что позволяет изучить и проиллюстрировать эффективность и возможности UPFC для увеличения мощности

Semiconductor optical amplifiers: performance and applications in optical packet switching [Invited]

Semiconductor optical amplifiers (SOAs) are a versatile core technology and the basis for the implementation of a number of key functionalities central to the evolution of highly wavelength-agile all-optical networks. We present an overview of the state of the art of SOAs and summarize a range of applications such as power boosters, preamplifiers, optical linear (gain-clamped) amplifiers, optical gates, and modules based on the hybrid integration of SOAs to yield high-level functionalities such as all-optical wavelength converters/regenerators and small space switching matrices. Their use in a number of proposed optical packet switching situations is also highlighted

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe