Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems

Traditionally, chaotic systems are built on the domain of infinite precision in mathematics. However, the quantization is inevitable for any digital devices, which causes dynamical degradation. To cope with this problem, many methods were proposed, such as perturbing chaotic states and cascading multiple chaotic systems. This paper aims at developing a novel methodology to design the higher-dimensional digital chaotic systems (HDDCS) in the domain of finite precision. The proposed system is based on the chaos generation strategy controlled by random sequences. It is proven to satisfy the Devaney's definition of chaos. Also, we calculate the Lyapunov exponents for HDDCS. The application of HDDCS in image encryption is demonstrated via FPGA platform. As each operation of HDDCS is executed in the same fixed precision, no quantization loss occurs. Therefore, it provides a perfect solution to the dynamical degradation of digital chaos.Comment: 12 page

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Analog readout for optical reservoir computers

Reservoir computing is a new, powerful and flexible machine learning technique that is easily implemented in hardware. Recently, by using a time-multiplexed architecture, hardware reservoir computers have reached performance comparable to digital implementations. Operating speeds allowing for real time information operation have been reached using optoelectronic systems. At present the main performance bottleneck is the readout layer which uses slow, digital postprocessing. We have designed an analog readout suitable for time-multiplexed optoelectronic reservoir computers, capable of working in real time. The readout has been built and tested experimentally on a standard benchmark task. Its performance is better than non-reservoir methods, with ample room for further improvement. The present work thereby overcomes one of the major limitations for the future development of hardware reservoir computers.Comment: to appear in NIPS 201

Optoelectronic Reservoir Computing

Reservoir computing is a recently introduced, highly efficient bio-inspired approach for processing time dependent data. The basic scheme of reservoir computing consists of a non linear recurrent dynamical system coupled to a single input layer and a single output layer. Within these constraints many implementations are possible. Here we report an opto-electronic implementation of reservoir computing based on a recently proposed architecture consisting of a single non linear node and a delay line. Our implementation is sufficiently fast for real time information processing. We illustrate its performance on tasks of practical importance such as nonlinear channel equalization and speech recognition, and obtain results comparable to state of the art digital implementations.Comment: Contains main paper and two Supplementary Material

Delayed Dynamical Systems: Networks, Chimeras and Reservoir Computing

We present a systematic approach to reveal the correspondence between time delay dynamics and networks of coupled oscillators. After early demonstrations of the usefulness of spatio-temporal representations of time-delay system dynamics, extensive research on optoelectronic feedback loops has revealed their immense potential for realizing complex system dynamics such as chimeras in rings of coupled oscillators and applications to reservoir computing. Delayed dynamical systems have been enriched in recent years through the application of digital signal processing techniques. Very recently, we have showed that one can significantly extend the capabilities and implement networks with arbitrary topologies through the use of field programmable gate arrays (FPGAs). This architecture allows the design of appropriate filters and multiple time delays which greatly extend the possibilities for exploring synchronization patterns in arbitrary topological networks. This has enabled us to explore complex dynamics on networks with nodes that can be perfectly identical, introduce parameter heterogeneities and multiple time delays, as well as change network topologies to control the formation and evolution of patterns of synchrony

Nanophotonic reservoir computing with photonic crystal cavities to generate periodic patterns

Reservoir computing (RC) is a technique in machine learning inspired by neural systems. RC has been used successfully to solve complex problems such as signal classification and signal generation. These systems are mainly implemented in software, and thereby they are limited in speed and power efficiency. Several optical and optoelectronic implementations have been demonstrated, in which the system has signals with an amplitude and phase. It is proven that these enrich the dynamics of the system, which is beneficial for the performance. In this paper, we introduce a novel optical architecture based on nanophotonic crystal cavities. This allows us to integrate many neurons on one chip, which, compared with other photonic solutions, closest resembles a classical neural network. Furthermore, the components are passive, which simplifies the design and reduces the power consumption. To assess the performance of this network, we train a photonic network to generate periodic patterns, using an alternative online learning rule called first-order reduced and corrected error. For this, we first train a classical hyperbolic tangent reservoir, but then we vary some of the properties to incorporate typical aspects of a photonics reservoir, such as the use of continuous-time versus discrete-time signals and the use of complex-valued versus real-valued signals. Then, the nanophotonic reservoir is simulated and we explore the role of relevant parameters such as the topology, the phases between the resonators, the number of nodes that are biased and the delay between the resonators. It is important that these parameters are chosen such that no strong self-oscillations occur. Finally, our results show that for a signal generation task a complex-valued, continuous-time nanophotonic reservoir outperforms a classical (i.e., discrete-time, real-valued) leaky hyperbolic tangent reservoir (normalized root-mean-square errors = 0.030 versus NRMSE = 0.127)

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

Design, Analysis, and Application of Flipped Product Chaotic System

In this paper, a novel method is proposed to build an improved 1-D discrete chaotic map called flipped product chaotic system (FPCS) by multiplying the output of one map with the output of a vertically flipped second map. Two variants, each with nine combinations, are shown with trade-off between computational cost and performance. The chaotic properties are explored using the bifurcation diagram, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient. The proposed schemes offer a wider chaotic range and improved chaotic performance compared to the constituent maps and several prior works of similar nature. Wide chaotic window and improved chaotic complexity are two desired characteristics for several security applications as these two characteristics ensure enhanced design space with elevated entropic properties. We present a general Field-Programmable Gate Array (FPGA) design framework for the hardware implementation of the proposed flipped-product schemes and the results show good qualitative agreement with the numerical results from MATLAB simulation. Finally, we present a new Pseudo Random Number Generator (PRNG) using the two variants of the proposed chaotic map and validate their excellent randomness property using four standard statistical tests, namely NIST, FIPS, TestU01, and Diehard