Design of wireless swallowable capsule with minimum power consumption and high resolution images

Medical technology has undergone major breakthroughs in recent years, especially in the area of the examination tools for diagnostic purposes. The traditional examination method for the diagnosis of gastrointestinal diseases is gastroscopy with the use of an endoscope. Wireless camera pill has created a new perspective for engineers and physicians. After years of great innovation, commercial swallowable pills have been produced and applied in clinical practice. These pills can cover the examination of the gastrointestinal system and provide to the physicians not only a lot more useful data that is not available from the traditional methods, but also elimination of the use of the painful endoscopy procedure. In this paper, a new design of the wireless swallowable pills has been proposed. It takes advantage of the benefits of every sub-system, like camera lenses, image compressor and RF sub-system. In this way our system can provide enough and accurate data to the physicians

Prediction-based incremental refinement for binomially-factorized discrete wavelet transforms

It was proposed recently that quantized representations of the input source (e. g., images, video) can be used for the computation of the two-dimensional discrete wavelet transform (2D DWT) incrementally. The coarsely quantized input source is used for the initial computation of the forward or inverse DWT, and the result is successively refined with each new refinement of the source description via an embedded quantizer. This computation is based on the direct two-dimensional factorization of the DWT using the generalized spatial combinative lifting algorithm. In this correspondence, we investigate the use of prediction for the computation of the results, i.e., exploiting the correlation of neighboring input samples (or transform coefficients) in order to reduce the dynamic range of the required computations, and thereby reduce the circuit activity required for the arithmetic operations of the forward or inverse transform. We focus on binomial factorizations of DWTs that include (amongst others) the popular 9/7 filter pair. Based on an FPGA arithmetic co-processor testbed, we present energy-consumption results for the arithmetic operations of incremental refinement and prediction-based incremental refinement in comparison to the conventional (nonrefinable) computation. Our tests with combinations of intra and error frames of video sequences show that the former can be 70% more energy efficient than the latter for computing to half precision and remains 15% more efficient for full-precision computation

A Vlsi architecture for lifting-based wavelet packet transform in fingerprint image compression

FBI uses a technique called Wavelet Scalar Quantization (WSQ), a wavelet packet transform (WPT) based method, to compress its fingerprint images. Though many VLSI architectures have been proposed for wavelet transform in the literature, it is not the case for the WPT. In this thesis, a VLSI architecture capable of computing the WPT is presented for application of WSQ. In the proposed architecture, Lifting Scheme (LS) is used to generate wavelets instead of the traditional convolution filter-bank (FB) specified in original standard. A comparative study between LS and FB shows that quality of images transformed by LS is completely acceptable (with 30dB∼40dB PSNR at a target bit rate of 0.75dpp) while fewer operations required. In particular, to compare with FB, the hardware consumption, for our WSQ application, is reduced to half due to the LS. Moreover, this architecture can be easily configured to compute any required WPT application

Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language

The wide spread of devices that use image processing in itsfunctions, like cellular phone and digital cameras, increases the need forspecialized processors for these functions as a replacement for softwareprograms that consume more time and resources. This paper presents ahardware description for discrete wavelet transform (DWT) module inVHDL language. The design involves the forward DWT (fDWT) and itsinverse (iDWT) characterized by variable number of transformation levels,ranging from one level to seven levels. Each one of these two modules isdesigned as hierarchical scheme that uses one-dimensional processingmodule twice to represent two-dimensional processing. The module can beused repeatedly on the same image for multilevel processing. Threeversions of the design are presented (v64, v128 and v256), each oneadapted different image size. Synthesis process showed that the designfrequency is about 56MHz. The simulation process showed that themaximum possible rounding error is about 0.012%. This resolution with thevariable number of processing level adapts this design to fit in manyapplications. Finally, a comparison of the proposed design with otherrelated work is presented, considering performance and specifications

Implementation of fingerprint based biometric system using optimized 5/3 DWT architecture and modified CORDIC based FFT

The real-time biometric systems are used to authenticate persons for wide range of security applications. In this paper, we propose implementation of fingerprint-based biometric system using Optimized 5/3 DWT architecture and Modified CORDIC-based Fast Fourier Transform (FFT). The Optimized 2D-DWT architecture is designed using Optimized 1D-DWT architectures, Memory Units and novel Controller Unit which is used to scan rows and columns of an image. The database fingerprint image is applied to the proposed Optimized 2D-DWT architecture to obtain four sub-bands of LL, LH, HL and HH. The efficient architecture of FFT is designed by using Modified CORDIC processor which generates twiddle factor angles of range – using Pre-processing Unit and Comparator Block. Further, the LL sub-band coefficients are applied to the Modified CORDIC based FFT to generate final fingerprint

Loop Transformations for the Optimized Generation of Reconfigurable Hardware

Current high-level design environments offer little support to implement data-intensive applications on heterogeneous-memory systems; they rather focus on parallelism. This thesis addresses the memory hierarchy problem to high-level transformations of loop structures. The composition of long transformation sequences by combining shorter subsequences is studied together with the influence of the order of applying transformation steps. Several methods are presented to estimate bounds on Ehrhart quasi-polynomials, which can be used to statically evaluate program properties, such as memory usage. Since loop transformations not only influence the data access pattern but also the control complexity we present a hardware loop controller architecture which supports hardware generation from the polyhedral representation used for loop transformations. The techniques are demonstrated by the semi-automatic generation of an FPGA implementation of an inverse discrete wavelet transform

FlexWAFE - eine Architektur für rekonfigurierbare-Bildverarbeitungssysteme

Recently there has been an increase in demand for high-resolution digital media content in both cinema and television industries. Currently existing equipment does not meet the requirements, or is too costly. New hardware systems and new programming techniques are needed in order to meet the high-resolution, high-quality, image requirements and reduce costs. The industry seeks a flexible architecture capable of running multiple applications on top of standard off-the-shelf components, with reduced development time. Until now, standard practice has been to develop specialized architectures and systems that target a single application. This has little flexibility and leads to high developments costs, every new application is designed almost from scratch. Our focus was to develop an architecture that is suited to image stream processing and has the flexibility to run multiple applications using the same FPGA-based hardware platform. The novelty in our approach is that we reconfigure parts of the architecture at run-time, but without incurring in the time and added constraints penalty of FPGA-partial-reconfiguration techniques. The architecture uses a hierarchical control structure that is well suited to parallel processing, and allows single cycle latency reconfiguration of parts of the processing pipeline. This is achieved using relatively little resources for the distributed control structures. To test the developed architecture a complex film-grain noise reduction algorithm was implemented on an off-the-shelf hardware platform developed by Thomson-Grass Valley. The system meet all the requirements and had very little load on the hierarchical control structures, there is growth headroom for much complexer control demands. The architecture has been ported to other hardware platforms, and other applications have been implemented as well. The run-time reconfigurability has proven to be a key factor in the success of the FlexWAFE.Kürzlich gab es eine Zunahme der Nachfrage nach hochauflösenden digitalen Medieninhalten in den Kino- und Fernsehenindustrien. Derzeit vorhandene Systeme entsprechen nicht den Anforderungen, oder sind zu teuer. Neue Hardware-Systeme und neuer Programmiertechniken sind erforderlich, um den hochauflösenden, hochwertigen, Bildanforderungen zu genügen und Kosten zu verringern. Die Industrie sucht eine flexible Architektur zur Ausführung mehrerer Anwendungen auf Standard-Komponenten, mit reduzierten Entwicklungszeiten. Bis jetzt ist gängige Praxis, spezialisierten Architektur und Systeme zu entwickeln, die eine einzelne Anwendung zielen. Dieses hat wenig Flexibilität und führt zu hohe Entwicklungskosten, jede neue Anwendung ist fast von Grund auf neu konzipiert. Unser Fokus war es, eine für Bild Verarbeitung geeignet Architektur zu entwickeln dass die Flexibilität hat mehrere Anwendungen an dieselbe FPGA-basierte Hardware-Plattform zu laufen. Die Neuheit in unserem Ansatz ist, dass wir Teile der Architektur zur Laufzeit rekonfigurieren, aber, ohne das Zeit und constraints strafe von FPGA Partielle-Rekonfiguration-Techniken. Die Architektur verwendet eine hierarchische Kontrollstruktur, die zur parallel Verarbeitung gut geeignet ist, und Single-Cycle-Latenz Rekonfiguration von Teilen der Verarbeitungs-Pipeline ermöglicht. Dieses wird unter Verwendung relativ weniger Ressourcen für die verteiltes Steuerung Strukturen erzielt. Um das entwickelte Architektur zu testen ein komplexer Film-Korn-Rauschunterdrückung Algorithmus wurde auf einer von Thomson-Grass Valley entwickelt standard Hardware-Plattform umgesetzt. Das System erfüllt alle Anforderungen und hatte sehr wenig Last auf den hierarchischen Kontrollstrukturen, es gibt viel Wachstum Spielraum für viel kompliziertere Steuerunganforderungen. Die Architektur ist zu anderen Hardwareplattformen portiert worden, und andere Anwendungen wurden ebenfalls implementiert. Der Laufzeitreconfigurability ist ein Schlüsselfaktor im Erfolg des FlexWAFE gewesen

New Transforms for JPEG Format

Diskrétní kosinová transformace je často používána v mnoha algoritmech při zpracování signálu. Tato transformace je také jádrem standardu JPEG, který je dosud nejpoužívanější formát pro ztrátovou kompresi obrazových dat. Od doby standardizace JPEGu byla publikována spousta dalších transformací, které se chovají obdobně jako diskrétní kosinová transformace. Cílem této práce je analyzovat využití těchto transformací v kompresním řetězci JPEGu. Každá transformace je zkoumána na základě její aplikace na datové sadě různých druhů obrázků a následného porovnání vůči ostatním transformacím za použití metriky PSNR a SSIM. Z měření vyplývá, že varianta DCT s přesahem bloku, lokální diskrétní kosinová transformace, má lepší výsledky při nižším datovém toku než diskrétní kosinová transformace. Při vyšším datovém toku má vlnková transformace Cohen-Daubechies-Feauveau 9/7 přibližně shodné výsledky s DCT.The discrete cosine transform (DCT) can be found in the heart of many image compression algorithms. Specifically, the JPEG format uses a lossy form of compression based on that transform. Since the standardization of the JPEG, many other transforms become practical in lossy data compression. This article aims to analyze the use of these transforms as the DCT replacement in the JPEG compression chain. Each transform is examined for different image datasets and subsequently compared to other transforms using the peak signal-to-noise ratio (PSNR) and SSIM. Our experiments show that an overlapping variation of the DCT, the local cosine transform (LCT), overcame the original block-wise transform at low bitrates. At high bitrates, the discrete wavelet transform employing the Cohen-Daubechies-Feauveau 9/7 wavelet offers about the same compression performance as the DCT.

Design and Evaluation of a Discrete Wavelet Transform Based Multi-Signal Receiver

General purpose receivers of today are designed with a broad bandwidth so that the receiver can accept a wide range of signal frequencies. These receivers usually accept one signal along with any interference that is included. To increase the signal detection capabilities of the wideband receiver, a design for a receiver that can detect two signals is needed. One of the requirements for this receiver is that the second weak signal needs to be processed in a timely manner so that the receiver can recognize it. To remedy the problem, a module was developed using wavelet-based techniques to remove spurs from the incoming signals to allow easier detection. The main basis for this concentration on wavelets comes from the way wavelets break down signals into portions (called resolutions) that allow easier determination of detail importance. Utilizing the multi-resolution attributes of the discrete wavelet transform, a way to remove signal spurs is made possible. When removing the signal noise from the signal, the two signal dynamic range of the system is increased, as this module is applied to multiple receiver systems for comparison of performance. Implementation of this system was originally done in C as well as MATLAB, but later is being implemented in VHDL with simulations done for verification of functionality