NEW MATERIAL FOR ELIMINATING LINEAR ENERGY TRANSFER SENSITIVITIES IN DEEPLY SCALED CMOS TECHNOLOGIES SRAM CELLS

As technology scales deep in submicron regime, CMOS SRAM memories have become increasingly sensitive to Single-Event Upset sensitivity. Key technological factors that impact Single-Event Upset sensitivity are gate length, gate and drain areas and the power supply voltage all of which impact transistor's nodal capacitance. In this work, I present engineering requirement studies, which show for the first time, the tread of Single-Event Upset sensitivity in deeply scaled SRAM cells. To mitigate the Single-Event Upset sensitivity, a novel approach is presented, illustrating exactly how material defects can be managed in a way that sets electrical resistance of the material as desired. A thin-film high-resistance value ranging from 2kΩ/-3.6MΩ/, and TCR of negative 0.0016%/˚C is presented. A defect model is presented that agrees well with the experimental results. These resistors are used in the cross-coupled latches; to decouple the latch nodes and delay the regenerative action of the cell, thus hardening against single even upset (SEU)

プレーナーガタオヨビフィンフェットガタエスラムニオケルチジョウホウシャセンキインシングルイベントアップセットニカンスルジッケンテキケンキュウ

T. Kato et al., "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization With Neutrons and Alpha Particles," in IEEE Transactions on Nuclear Science, vol. 68, no. 7, pp. 1436-1444, July 2021, doi: 10.1109/TNS.2021.3082559

Design, implementation and testing of SRAM based neutron detectors

Neutrons of thermal and high energies can change the value of a bit stored in a Static Random Access Memory (SRAM) memory chip. The effect is non destructive and linearly dependent on the amount of incoming particles, which makes it exploitable for use as a neutron detector. Detection is done by writing a known pattern to the memory and continuously reading it back checking for wrong values. As the SRAM memory is immune to gamma radiation it is ideal for use in for instance medical linear accelerators for detection of neutron dose to a patient. The intention of this work has been twofold: (1) Testing of different SRAM devices of different bit-sizes, manufacturers, feature sizes and voltages for their sensitivity to neutrons of different energies from thermal to high energies. (2) Design and implement detector hardware, firmware and its accompanying readout system for successful use in irradiation testing. The work has been done in close collaboration with Eivind Larsen, whose main contributions has been related to the nuclear physics aspect of the work in addition to arrangements in regard to beam setup and experimentation. Testing have been done at the Physikalisch-Technische Bundesanstalt (PTB) facility in Braunschweig Germany in a quasi-monochromatic neutron beam of 5:8MeV, 8:5MeV and 14:8MeV, finding a dependence of the sensitivity on the energy. In addition there have been testing conducted in the high energy hadron field at CERF at CERN, finding that by using the results from the other experiments an estimated range of the saturation cross section could be determined. Testing was also conducted at two occasions in the 29MeV proton beam at Oslo Cyclotron Laboratory (OCL) in Oslo Norway, where it was found that the detector could be used as a reference detector for beam monitoring and for beam profile characterization. The cross sections of the detectors were found to be comparable to the 14:8MeV cross section found at PTB. Thermal neutron testing of the devices was done in the thermal neutron field of the nuclear reactor at Institute for Energy Technology (IFE) at Kjeller Norway. All the devices were found to be sensitive to the field. Detector electronics, adapted to the different devices, has been built which can withstand the same radiation as the memory device without malfunctioning. There has been a focus on using Commercial Off The Shelf (COTS) components for reducing the total cost of the detector to about 100-200$US. The use of COTS SRAM memory devices also simplifies the reproducibility and availability of spares. The detector currently uses a two way communication between the detector and iv Abstract the readout computer over two pair of cables reducing the amount of cabling needed for experiments. The detectors can be connected to the communication link in a bus fashion, currently enabling a total of 14 detectors to be tested simultaneously from 100m away, over the same cable. Single Event Latch-up (SEL) and problems with irregular count rate of SRAMs created in the 90nm fabrication node has created problems during testing. Some solutions and techniques to mitigate these in hardware and firmware are presented in this work.Master i FysikkMAMN-PHYSPHYS39

Proton-and Neutron-Induced Single-Event Upsets in FPGAs for the PANDA Experiment

Single-event upsets (SEUs) affecting the configuration memory of a 28-nm field-programmable gate array (FPGA) have been studied through experiments and Monte Carlo modeling. This FPGA will be used in the front-end electronics of the electromagnetic calorimeter in PANDA (Antiproton Annihilation at Darmstadt), an upcoming hadron-physics experiment. Results from proton and neutron irradiations of the FPGA are presented and shown to be in agreement with previous experimental results. To estimate the mean time between SEUs during operation of PANDA, a Geant4-based Monte Carlo model of the phenomenon has been used. This model describes the energy deposition by particles in a silicon volume, the subsequent drift and diffusion of charges in the FPGA memory cell, and the eventual collection of charges in the sensitive regions of the cell. The values of the two free parameters of the model, the sensitive volume side d = 87 nm and the critical charge Qcrit = 0.23 fC, were determined by fitting the model to the experimental data. The results of the model agree well with both the proton and neutron data and are also shown to correctly predict the cross sections for upsets induced by other particles. The model-predicted energy dependence of the cross section for neutron-induced upsets has been used to estimate the rate of SEUs during initial operation of PANDA. At a luminosity of 1&amp;cdot; 1031 cm-2s-1, the predicted mean time between upsets (MTBU) is between 120 and 170 h per FPGA, depending on the beam momentum.</p

Terrestrial Cosmic Ray Induced Soft Errors and Large-Scale FPGA Systems in the Cloud

Radiation from outer space can cause soft errors in microelectronic devices deployed at terrestrial altitudes on Earth. Cosmic rays entering the Earth’s atmosphere create a complex cascade of radioactive particles. The most likely form of cosmic radiation to cause soft errors in microelectronics at terrestrial levels are neutrons. SRAM-based FPGAs are susceptible to terrestrial cosmic ray induced soft errors. These soft errors occur infrequently for a single device deployed at terrestrial altitudes. When many FPGAs are deployed in a large-scale system, the impact of these soft errors on reliability can be significant. This study examines terrestrial cosmic ray induced soft errors and the effects they can have on large-scale deployment of FPGAs in cloud computing. Fifteen data-center-like designs were tested for sensitivity through fault injecting. Sensitivities ranged from less than 1% to about 12% of randomly injected faults resulting in unacceptable behavior. A hypothetical but realistic large-scale FPGA system, with 100,000 node deployed at a high-altitude, running the most sensitive design would experience the dominant failure mode of silent data corruption every 3.8 hours on average. This system would only be able to retain reliability level above 0.99 for about two minutes. Some soft error detection and recover approaches are discussed

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65nm CMOS Bulk SRAMs

The power consumption of Static Random Access Memory (SRAM) has become an important issue for modern integrated circuit design, considering the fact that they occupy large area and consume significant portion of power consumption in modern nanometer chips. SRAM operating in low power supply voltages has become an effective approach in reducing power consumption. Therefore, it is essential to experimentally characterize the single event effects (SEE) of hardened and unhardened SRAM cells to determine their appropriate applications, especially when a low supply voltage is preferred. In this thesis, a SRAM test chip was designed and fabricated with four cell arrays sharing the same peripheral circuits, including two types of unhardened cells (standard 6T and sub-threshold 10T) and two types of hardened cells (Quatro and DICE). The systems for functional and radiation tests were built up with power supply voltages that ranged from near threshold 0.4 V to normal supply 1 V. The test chip was irradiated with alpha particles and heavy ions with various linear energy transfers (LETs) at different core supply voltages, ranging from 1 V to 0.4 V. Experimental results of the alpha test and heavy ion test were consistent with the results of the simulation. The cross sections of 6T and 10T cells present much more significant sensitivities than Quatro and DICE cells for all tested supply voltages and LET. The 10T cell demonstrates a more optimal radiation performance than the 6T cell when LET is small (0.44 MeV·cm2/mg), yet no significant advantage is evident when LET is larger than this. In regards to the Quatro and DICE cells, one does not consistently show superior performance over the other in terms of soft error rates (SERs). Multi-bit upsets (MBUs) occupy a larger portion of total SEUs in DICE cell when relatively larger LET and smaller supply voltage are applied. It explains the loss in radiation tolerance competition with Quatro cell when LET is bigger than 9.1 MeV·cm2/mg and supply voltage is smaller than 0.6 V. In addition, the analysis of test results also demonstrated that the error amount distributions follow a Poisson distribution very well for each type of cell array

Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology

Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting in voltage and current perturbation, where errors are induced. This phenomenon is termed a Single Event Effect (SEE). With the shrinking of transistor size, charge sharing between adjacent devices leads to less effectiveness of current radiation hardening methods. Improving fault-tolerance of storage cells and logic gates in advanced technologies becomes urgent and important. A new Single Event Upset (SEU) tolerant latch is proposed based on a previous hardened Quatro design. Soft error analysis tools are used and results show that the critical charge of the proposed design is approximately 2 times higher than that of the reference design with negligible penalty in area, delay, and power consumption. A test chip containing the proposed flip-flop chains was designed and exposed to alpha particles as well as heavy ions. Radiation experimental results indicate that the soft error rates of the proposed design are greatly reduced when Linear Energy Transfer (LET) is lower than 4, which makes it a suitable candidate for ground-level high reliability applications. To improve radiation tolerance of combinational circuits, two combinational logic gates are proposed. One is a layout-based hardening Cascode Voltage Switch Logic (CVSL) and the other is a fault-tolerant differential dynamic logic. Results from a SEE simulation tool indicate that the proposed CVSL has a higher critical charge, less cross section, and shorter Single Event Transient (SET) pulses when compared with reference designs. Simulation results also reveal that the proposed differential dynamic logic significantly reduces the SEU rate compared to traditional dynamic logic, and has a higher critical charge and shorter SET pulses than reference hardened design

Cross-layer Soft Error Analysis and Mitigation at Nanoscale Technologies

This thesis addresses the challenge of soft error modeling and mitigation in nansoscale technology nodes and pushes the state-of-the-art forward by proposing novel modeling, analyze and mitigation techniques. The proposed soft error sensitivity analysis platform accurately models both error generation and propagation starting from a technology dependent device level simulations all the way to workload dependent application level analysis

Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation

The AMD UltraScale+ XCZU9EG device is a Multi-Processor System-on-Chip (MPSoC) with embedded Programmable Logic (PL) that excels in many Edge (e.g., automotive or avionics) and Cloud (e.g., data centres) terrestrial applications. However, it incorporates a large amount of SRAM cells, making the device vulnerable to Neutron-induced Single Event Upsets (NSEUs) or otherwise soft errors. Semiconductor vendors incorporate soft error mitigation mechanisms to recover memory upsets (i.e., faults) before they propagate to the application output and become an error. But how effective are the MPSoC's mitigation schemes? Can they effectively recover upsets in high altitude or large scale applications under different workloads? This article answers the above research questions through a solid study that entails accelerated neutron radiation testing and dependability analysis. We test the device on a broad range of workloads, like multi-threaded software used for pose estimation and weather prediction or a software/hardware (SW/HW) co-design image classification application running on the AMD Deep Learning Processing Unit (DPU). Assuming a one-node MPSoC system in New York City (NYC) at 40k feet, all tested software applications achieve a Mean Time To Failure (MTTF) greater than 148 months, which shows that upsets are effectively recovered in the processing system of the MPSoC. However, the SW/HW co-design (i.e., DPU) in the same one-node system at 40k feet has an MTTF = 4 months due to the high failure rate of its PL accelerator, which emphasises that some MPSoC workloads may require additional NSEU mitigation schemes. Nevertheless, we show that the MTTF of the DPU can increase to 87 months without any overhead if one disregards the failure rate of tolerable errors since they do not affect the correctness of the classification output.Comment: This manuscript is under review at IEEE Transactions on Reliabilit

INTEGRATED CIRCUITS FOR HIGH ENERGY PHYSICS EXPERIMETNS

Integrated Circuits are used in most people\u2019s lives in the modern societies. An important branch of research and technology is focused on Integrated Circuit (IC) design, fabrication, and their efficient applications; moreover most of these activities are about commercial productions with applications in ambient environment. However the ICs play very important role in very advance research fields, as Astronomy or High Energy Physics experiments, with absolutely extreme environments which require very interdisciplinary research orientations and innovative solutions. For example, the Fast TracKer (FTK) electronic system, which is an important part of triggering system in ATLAS experiment at European Organization for Nuclear Research (CERN), in every second of experiment selects 200 interesting events among 40 millions of total events due to collision of accelerated protons. The FTK function is based on ICs which work as Content Addressable Memory (CAM). A CAM compares the income data with stored data and gives the addresses of matching data as an output. The amount of calculation in FTK system is out of capacity of commercial ICs even in very advanced technologies, therefore the development of innovative ICs is required. The high power consumption due to huge amount of calculation was an important limitation which is overcome by an innovative architecture of CAM in this dissertation. The environment of ICs application in astrophysics and High Energy Physics experiments is different from commercial ICs environment because of high amount of radiation. This fact started to get seriously attention after the first \u201cTelstar I\u201d satellite failure because of electronic damages due to radiation effects in space, and opened a new field of research mostly about radiation hard electronics. The multidisciplinary research in radiation hard electronic field is about radiation effects on semiconductors and ICs, deep understanding about the radiation in the extreme environments, finding alternative solutions to increase the radiation tolerance of electronic components, and development of new simulation method and test techniques. Chapter 2 of this dissertation is about the radiation effects on Silicon and ICs. Moreover, In this chapter, the terminologies of radiation effects on ICs are explained. In chapter 3, the space and high energy physics experiments environments, which are two main branches of radiation hard electronics research, are studied. The radiation tolerance in on-chip circuits is achieving by two kinds of methodology: Radiation Hardening By Process (RHBP) and Radiation Hardening By Design (RHBD). RHBP is achieved by changing the conventional fabrication process of commercial ICs. RHBP is very expensive so it is out of budget for academic research, and in most cases it is exclusive for military application, with very restricted rules which make the access of non-military organizations impossible. RHBD with conventional process is the approach of radiation hard IC design in this dissertation. RHBD at hardware level can be achieved in different ways: \u2022 System level RHBD: radiation hardening at system level is achieved by algorithms which are able to extract correct data using redundant information. \u2022Architecture level RHBD: some hardware architectures are able to prevent of lost data or mitigate the radiation effects on stored data without interfacing of software. Error Correction Code (ECC) circuits and Dual Interlocked storage CEll (DICE) architecture are two examples of RHBD at architecture level. \u2022 Circuit level RHBD: at circuit level, some structures are avoided or significantly reduced. For example, feedback loops with high gain are very sensitive to radiation effects. \u2022 Layout level RHBD: there are also different solutions in layout design level to increase the radiation tolerance of circuits. Specific shapes of transistor design, optimization of the physical distance between redundant data and efficient polarization of substrate are some techniques commonly used to increase significantly the radiation tolerance of ICs. An innovative radiation hard Static Random Access Memory (SRAM), designed in three versions, is presented in chapter 4. The radiation hardening is achieved by RHBD approach simultaneously at architecture, circuit and layout levels. Complementary Metal-Oxide-Semiconductor (CMOS) 65 nm is the technology of design and the prototype chip is fabricated at Taiwan Semiconductor Manufacturing Company (TSMC). Chapter 5 is about the development of simulation models that can help to predict the radiation effect in the behavior of SRAM block. The setup system developed to characterize the radiation hard SRAM prototype chip is presented in Chapter 5. The setup system gives the possibility of testing the prototype exposed under radiation in a vacuum chamberand regular laboratory environment. Chapter 6 is about the contribution of this dissertation on FTK project and the conclusion of all research activities is shown in the final part of this dissertation. The research activities of this dissertation in supported by Italian National Institute for Nuclear Physics (INFN) as part of CHIPIX65 project and RD53 collaboration at CERN