The PreAmplifier ShAper for the ALICE TPC-Detector

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18-25 pF. For an input capacitance of 25 pF, the PASA features a conversion gain of 12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of 11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit recovers smoothly to the baseline in about 600 ns. An integral non-linearity of 0.19% with an output swing of about 2.1 V is also achieved. The total area of the chip is 18 mm$^2$ and is implemented in AMS's C35B3C1 0.35 micron CMOS technology. Detailed characterization test were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA has demonstrated to fulfill all requirements

Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

Performance evaluation of non-prefiltering vs. time reversal prefiltering in distributed and uncoordinated IR-UWB ad-hoc networks

Time Reversal (TR) is a prefiltering scheme mostly analyzed in the context of centralized and synchronous IR-UWB networks, in order to leverage the trade-off between communication performance and device complexity, in particular in presence of multiuser interference. Several strong assumptions have been typically adopted in the analysis of TR, such as the absence of Inter-Symbol / Inter-Frame Interference (ISI/IFI) and multipath dispersion due to complex signal propagation. This work has the main goal of comparing the performance of TR-based systems with traditional non-prefiltered schemes, in the novel context of a distributed and uncoordinated IR-UWB network, under more realistic assumptions including the presence of ISI/IFI and multipath dispersion. Results show that, lack of power control and imperfect channel knowledge affect the performance of both non-prefiltered and TR systems; in these conditions, TR prefiltering still guarantees a performance improvement in sparse/low-loaded and overloaded network scenarios, while the opposite is true for less extreme scenarios, calling for the developement of an adaptive scheme that enables/disables TR prefiltering depending on network conditions