A high aspect ratio Fin-Ion Sensitive Field Effect Transistor: compromises towards better electrochemical bio-sensing

The development of next generation medicines demand more sensitive and reliable label free sensing able to cope with increasing needs of multiplexing and shorter times to results. Field effect transistor-based biosensors emerge as one of the main possible technologies to cover the existing gap. The general trend for the sensors has been miniaturisation with the expectation of improving sensitivity and response time, but presenting issues with reproducibility and noise level. Here we propose a Fin-Field Effect Transistor (FinFET) with a high heigth to width aspect ratio for electrochemical biosensing solving the issue of nanosensors in terms of reproducibility and noise, while keeping the fast response time. We fabricated different devices and characterised their performance with their response to the pH changes that fitted to a Nernst-Poisson model. The experimental data were compared with simulations of devices with different aspect ratio, stablishing an advantage in total signal and linearity for the FinFETs with higher aspect ratio. In addition, these FinFETs promise the optimisation of reliability and efficiency in terms of limits of detection, for which the interplay of the size and geometry of the sensor with the diffusion of the analytes plays a pivotal role.Comment: Article submitted to Nano Letter

Static random-access memory designs based on different FinFET at lower technology node (7nm)

Title from PDF of title page viewed January 15, 2020Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (page 50-57)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] – [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] – [13] and biomedical [17] –[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] – [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications.Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMS -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future wor

Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications

Continuous scaling of CMOS technology has now reached a state of evolution, therefore, novel device structures and new materials have been proposed for this purpose. The Screen- Grid field Effect Transistor is introduced as a as a novel device structure that takes advantage of several innovative aspects of the FinFET while introducing new geometrical feature to improve a FET device performance. The idea is to design a FET which is as small as possible without down-scaling issues, at the same time satisfying optimum device performance for both analogue and digital applications. The analogue operation of the SGrFET shows some promising results which make it interesting to continue the investigation on SGrFET for digital applications. The SGrFET addresses some of the concerns of scaled CMOS such as Drain Induce Barrier Lowering and sub-threshold slope, by offering the superior short channel control. In this work in order to evaluate SGrFET performance, the proposed device compared to the classical MOSFET and provides comprehensive benchmarking with finFETs. Both AC and DC simulations are presented using TaurusTM and MediciTM simulators which are commercially available via Synopsis. Initial investigation on the novel device with the single gate structure is carried out. The multi-geometrical characteristic of the proposed device is used to reduce parasitic capacitance and increase ION/IOFF ratio to improve device performance in terms of switching characteristic in different circuit structures. Using TaurusTM AC simulation, a small signal circuit is introduced for SGrFET and evaluated using both extracted small signal elements from TaurusTM and Y-parameter extraction. The SGrFET allows for the unique behavioural characteristics of an independent-gate device. Different configurations of double-gate device are introduced and benchmark against the finFET serving as a double gate device. Five different logic circuits, the complementary and N-inverter, the NOR, NAND and XOR, and controllable Current Mirror circuits are simulated with finFET and SGrFET and their performance compared. Some digital key merits are extracted for both finFET and SGrFET such as power dissipation, noise margin and switching speed to compare the devices under the investigation performance against each other. It is shown that using multi-geometrical feature in SGrFET together with its multi-gate operation can greatly decrease the number of device needed for the logic function without speed degradation and it can be used as a potential candidate in mix-circuit configuration as a multi-gate device. The initial fabrication steps of the novel device explained together with some in-house fabrication process using E-Beam lithography. The fabricated SGrFET is characterised via electrical measurements and used in a circuit configuration

Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Design of SRAM Cell using Modified Lector and Dual Threshold Method Based on FINFET

FinFET (Fin Field Effect Transistor) is a new technology that satisfies the demand for a superior storage system by improving transistor circuit design (SS). CMOS devices experience a wide range of issues due to the gate's diminishing ability to control the channel. Increased total production costs are a few of these disadvantages. But this store needs to dissipate less power, have a quick access time, and a low leakage current. The increased power dissipation and leakage current of traditional CMOS-based SRAM (Static RAM) architectures cause a sharp decline in performance. The nanoscale gadget called FinFET is being introduced for use in SRAM fabrication due to its 3D gate architecture. The adoption of FinFET has helped boost overall performance in terms of efficiency, power, and footprint. And because it is immune to SCEs, FinFET has become the transistor of choice. In this study, we have examined a number of FinFET-based SRAM cells and compared them with CMOS technology. We have also suggested a novel 14T SRAM design that uses the Dual Threshold Method and Modified Lector Approach with FinFET, and it is implemented for the 1bit, 4bit, and 8bit

Low Leakage and PDP Optimized FinFET based 8T SRAM Design

The paper proposes a Fin Field Effect Transistors (FinFETs) based SRAM design comprising of 8 transistors. The circuit utilizes channel length of 22 nanometers. The operation of this circuit is dependent upon the control switch CS that decides the operating mode and minimizes the leakage current flowing in the cell which in turn lowers the leakage power to a minimal value of 0.331pW. The read buffer available in the design provides a different path for read mode and also enhances the Read Static Noise Margin (RSNM), thus enhancing the readability of the circuit.This design is also able to operate at a minimal voltage of 70mV, thus efficiently utilizing the power available. It also optimizes the power delay product (PDP) for both read and write operations

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio