Wireless neural recording with single low-power integrated circuit

Journal ArticleWe present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor

Pipelined Two-Operand Modular Adders

Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The design of pipelined TOMAs is usually obtained by inserting an appriopriate number of latch layers inside a nonpipelined TOMA structure. Hence their area is also determined by the number of latches and the delay by the number of latch layers. In this paper we propose a new pipelined TOMA that is based on a new TOMA, that has the smaller area and smaller delay than other known structures. Comparisons are made using data from the very large scale of integration (VLSI) standard cell library

Design and low-power implementation of an adaptive image rejection receiver

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures

Steganography: a class of secure and robust algorithms

This research work presents a new class of non-blind information hiding algorithms that are stego-secure and robust. They are based on some finite domains iterations having the Devaney's topological chaos property. Thanks to a complete formalization of the approach we prove security against watermark-only attacks of a large class of steganographic algorithms. Finally a complete study of robustness is given in frequency DWT and DCT domains.Comment: Published in The Computer Journal special issue about steganograph

ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

Gunn Effect in Silicon Nanowires: Charge Transport under High Electric Field

Gunn (or Gunn-Hilsum) Effect and its associated negative differential resistivity (NDR) emanates from transfer of electrons between two different energy bands in a semiconductor. If applying a voltage (electric field) transfers electrons from an energy sub band of a low effective mass to a second one with higher effective mass, then the current drops. This manifests itself as a negative slope or NDR in the I-V characteristics of the device which is in essence due to the reduction of electron mobility. Recalling that mobility is inversely proportional to electron effective mass or curvature of the energy sub band. This effect was observed in semiconductors like GaAs which has direct bandgap of very low effective mass and its second indirect sub band is about 300 meV above the former. More importantly a self-repeating oscillation of spatially accumulated charge carriers along the transport direction occurs which is the artifact of NDR, a process which is called Gunn oscillation and was observed by J. B. Gunn. In sharp contrast to GaAs, bulk silicon has a very high energy spacing (~1 eV) which renders the initiation of transfer-induced NDR unobservable. Using Density Functional Theory (DFT), semi-empirical 10 orbital ($sp^{3}d^{5}s^{*}$) Tight Binding (TB) method and Ensemble Monte Carlo (EMC) simulations we show for the first time that (a) Gunn Effect can be induced in narrow silicon nanowires with diameters of 3.1 nm under 3 % tensile strain and an electric field of 5000 V/cm, (b) the onset of NDR in I-V characteristics is reversibly adjustable by strain and (c) strain can modulate the value of resistivity by a factor 2.3 for SiNWs of normal I-V characteristics i.e. those without NDR. These observations are promising for applications of SiNWs in electromechanical sensors and adjustable microwave oscillators.Comment: 18 pages, 6 figures, 63 reference

Confession Session: Learning from Others Mistakes

Accepted versio

Improved Reliability of FPGA-based PUF Identification Generator Design

Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n -bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25°C to 70°C with ± 10% variation in the supply voltage. </jats:p