Design Considerations of Data Converters for Industrial Technology

This paper presents circuit design considerations of high resolution data converters applied for industrial technology, some important design issues related to filter in analog-to-digital converters (ADCs) are discussed. Whole design flow about filter is given in this work and the design considerations mentioned in this paper are useful for the industrial practice and applications of high resolution ADC, finally, a practical design is illustrated with discussion of ΣΔ modulator

Memristive Non-Volatile Memory Based on Graphene Materials

Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices

RFIC piirin digitaaliohjaukseen vaadittavien piirirakenteiden suunnittelu

Tiivistelmä. Tässä työssä suunnitellaan 22 nm FD-SOI-prosessille digitaalikirjaston osa, jolla voidaan toteuttaa tarvittava ohjaus RFIC-komponenttilohkoille. Komponenteista rakennetaan mahdollisimman pieniä ja nopeita käyttäen matalan kynnysjännitteen transistoreja. Työssä tarvittavan digitaalisen ohjauksen luomiseksi tehdään NAND-, NOR-, AND- ja NOT-portit sekä siirtorekistereitä, osoitedekooderi, virta-DAC ja D-kiikku. Piirikaaviot ja -kuviot suunnitellaan Cadencen Virtuoso-ohjelmistolla ja simuloinnit tehdään Cadencen ADE-simulointiympäristössä. Simulointien avulla mitoitetaan digitaalilohkot ja varmistetaan niiden toiminta. Testipenkkeihin luodaan lohkoille mahdollisimman todenmukainen ympäristö käyttäen viivästettyjä ja noin 5 ps nousu- ja laskuajoilla olevia signaaleja sekä kuormana 5 minimikokoista invertteriä. Tehonkulutus ja pinta-ala minimoidaan suunnittelemalla mahdollisimman nopeita ja pieniä piirejä ja käyttäen vain muutamaa alinta metallikerrosta piirikuviossa. Transistoreja yhdistelemällä piirin pinta-alaa saadaan parhaissa tapauksissa pienennettyä yli 50%. Simuloinneissa nähdään, että komponenttien tehonkulutus ja teknologian tuomat virtarajoitukset eivät tuota ongelmia, sillä komponenttien maksimivirrat pysyvät alle 500 µA. Lisäksi simuloinneissa tulee esille logiikkakomponenttien kyky vaimentaa kohinaa ja kapasitiivisen kuormituksen vaikutus virtaan ja viiveeseen. Lopuksi valmiit komponentit simuloidaan vielä RFIC-lohkon kanssa piirikaaviotasolla ekstraktoitujen parasiittisten vaikutus huomioiden.Design of circuit blocks for digital control of integrated RF circuit. Abstract. The aim of this work is to design a part of a digital component library using 22 nm FDSOI CMOS process, which could be used to digitally control analog RFIC-blocks. Low threshold voltage transistors are used in order to create as small and fast components as possible. In this work NAND, NOR, AND and NOT logic ports are designed together with shift registers, address decoder, current-DAC and D-flipflop. Schematics and layouts are designed by using Cadence Virtuoso software and simulations are done by using Cadence ADE -simulation environment. Simulations are used to size logic components and verify operations. A realistic operation environment is created by using delayed signals with 5 ps rise and fall times and a load of 5 minimum size inverters. Power consumption and area of circuits are minimized by designing fast and small circuits and by using only a few of the bottom metal layers in layouts. In the best cases the area is reduced more than 50 percent by combining transistor structures. In simulations power consumption and current constraints imposed by used technology are not a problem due to smaller than 500 µA maximum currents of components. In addition, the simulations show the ability of logic components to attenuate noise and how the capacitive load affects to the current consumption and delay of components. Finally, implemented components are simulated with actual RFIC-blocks at schematic level by considering the effects of extracted parasitic components

3D GaN nanoarchitecture for field-effect transistors

The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications

RISC-Vコンピュータシステムに基づくシリコンレベルの信頼ルートを有する信頼できる実行環境

電気通信大学202

Analysis and design considerations of resonator arrays for inductive power transfer systems

In the frame of inductive power transfer (IPT) systems, arrays of magnetically coupled resonators have received increasing attention as they are cheap and versatile due to their simple structure. They consist of magnetically coupled coils, which resonate with their self-capacitance or lumped capacitive networks. Of great industrial interest are planar resonator arrays used to power a receiver that can be placed at any position above the array. A thorough circuit analysis has been carried out, first starting from traditional two-coil IPT devices. Then, resonator arrays have been introduced, with particular attention to the case of arrays with a receiver. To evaluate the system performance, a circuit model based on original analytical formulas has been developed and experimentally validated. The results of the analysis also led to the definition of a new doubly-fed array configuration with a receiver that can be placed above it at any position. A suitable control strategy aimed at maximising the transmitted power and the efficiency has been also proposed. The study of the array currents has been carried out resorting to the theory of magneto-inductive waves, allowing useful insight to be highlighted. The analysis has been completed with a numerical and experimental study on the magnetic field distribution originating from the array. Furthermore, an application of the resonator array as a position sensor has been investigated. The position of the receiver is estimated through the measurement of the array input impedance, for which an original analytical expression has been also obtained. The application of this sensing technique in an automotive dynamic IPT system has been discussed. The thesis concludes with an evaluation of the possible applications of two-dimensional resonator arrays in IPT systems. These devices can be used to improve system efficiency and transmitted power, as well as for magnetic field shielding