Chip level simulation of fault tolerant computers

Chip level modeling techniques, functional fault simulation, simulation software development, a more efficient, high level version of GSP, and a parallel architecture for functional simulation are discussed

Advanced flight computer. Special study

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort

FTDD973: A multimedia knowledge-based system and methodology for operator training and diagnostics

FTDD973 (973 Fabricator Training, Documentation, and Diagnostics) is an interactive multimedia knowledge based system and methodology for computer-aided training and certification of operators, as well as tool and process diagnostics in IBM's CMOS SGP fabrication line (building 973). FTDD973 is an example of what can be achieved with modern multimedia workstations. Knowledge-based systems, hypertext, hypergraphics, high resolution images, audio, motion video, and animation are technologies that in synergy can be far more useful than each by itself. FTDD973's modular and object-oriented architecture is also an example of how improvements in software engineering are finally making it possible to combine many software modules into one application. FTDD973 is developed in ExperMedia/2; and OS/2 multimedia expert system shell for domain experts

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

Technological development, strategic behavior and government policy in information technology industries

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Political Science, 1989.Includes bibliographical references.by Charles H. Ferguson.Ph.D

Jitter measurement built-in self-test circuit for phase locked loops

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 77-79).This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.by Brandon Ray Kam.M.Eng