Simulations of Implementation of Advanced Communication Technologies

Wireless communication systems have seen significant advancements with the introduction of 3G, 4G, and 5G mobile standards. Since the simulation of entire systems is complex and may not allow evaluation of the impact of individual techniques, this thesis presents techniques and results for simulating the performance of advanced signaling techniques used in 3G, 4G, and 5G systems, including Code division multiple access (CDMA), Multiple Input Multiple Output (MIMO) systems, and Low-Density Parity Check (LDPC) codes. One implementation issue that is explored is the use of quantized Analog to Digital Converter (ADC) outputs and their impact on system performance. Code division multiple access (CDMA) is a popular wireless technique, but its effectiveness is limited by factors such as multiple access interference (MAI) and the near far effect (NFE). The joint effect of sampling and quantization on the analog-digital converter (ADC) at the receiver\u27s front end has also been evaluated for different quantization bits. It has been demonstrated that 4 bits is the minimum ADC resolution sensitivity required for a reliable connection for a quantized signal with 3- and 6-dB power levels in noisy and interference-prone environments. The demand for high data rate, reliable transmission, low bit error rate, and maximum transmission with low power has increased in wireless systems. Multiple Input Multiple Output (MIMO) systems with multiple antennas at both the transmitter and receiver side can meet these requirements by exploiting diversity and multipath propagation. The focus of MIMO systems is on improving reliability and maximizing throughput. Performance analysis of single input single output (SISO), single input multiple output (SIMO), multiple input single output (MISO), and MIMO systems is conducted using Alamouti space time block code (STBC) and Maximum Ratio Combining (MRC) technique used for transmit and receive diversity for Rayleigh fading channel under AWGN environment for BPSK and QPSK modulation schemes. Spatial Multiplexing (SM) is used to enhance spectral efficiency without additional bandwidth and power requirements. Minimum mean square error (MMSE) method is used for signal detection at the receiver end due to its low complexity and better performance. The performance of MIMO SM technique is compared for different antenna configurations and modulation schemes, and the MMSE detector is employed at the receiving end. Advanced error correction techniques for channel coding are necessary to meet the demand for Mobile Internet in 5G wireless communications, particularly for the Internet of Things. Low Density Parity Check (LDPC) codes are used for error correction in 5G, offering high coding gain, high throughput, low latency, low power dissipation, low complexity, and rate compatibility. LDPC codes use base matrices of 5G New Radio (NR) for LDPC encoding, and a soft decision decoding algorithm is used for efficient Frame Error Rate (FER) performance. The performance of LDPC codes is assessed using a soft decision decoding layered message passing algorithm, with BPSK modulation and AWGN channel. Furthermore, the effects of quantization on LDPC codes are analyzed for both small and large numbers of quantization bits

Von Neumann bottlenecks in non-von Neumann computing architectures

The term "neuromorphic" refers to a broad class of computational devices that mimic various aspects of cortical information processing. In particular, they instantiate neurons, either physically or virtually, which communicate through time-singular events called spikes. This thesis presents a generic RTL implementation of a Point-to-Point chip interconnect protocol that is well-suited to accommodate the unique I/O requirements associated with event-based communication, especially in the case of accelerated mixed-signal neuromorphic devices. A physical realization of such an interconnect was implemented on the most recent version of the BrainScaleS-2 architecture---the HICANN-X system---to facilitate a high-speed bi-directional connection to a host FPGA. Event rates of up to 250MHz full-duplex as well as several stream-secured configuration and memory interface channels are transported via 8*1Gbit/s LVDS DDR serializers. As the presented approach is entirely independent of the serializer implementation, it has applications beyond neuromorphic computing, such as enabling the separation of concerns and aiding the development of serializer-independent protocol bridges for system design

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Doctor of Philosophy

dissertationCommunication surpasses computation as the power and performance bottleneck in forthcoming exascale processors. Scaling has made transistors cheap, but on-chip wires have grown more expensive, both in terms of latency as well as energy. Therefore, the need for low energy, high performance interconnects is highly pronounced, especially for long distance communication. In this work, we examine two aspects of the global signaling problem. The first part of the thesis focuses on a high bandwidth asynchronous signaling protocol for long distance communication. Asynchrony among intellectual property (IP) cores on a chip has become necessary in a System on Chip (SoC) environment. Traditional asynchronous handshaking protocol suffers from loss of throughput due to the added latency of sending the acknowledge signal back to the sender. We demonstrate a method that supports end-to-end communication across links with arbitrarily large latency, without limiting the bandwidth, so long as line variation can be reliably controlled. We also evaluate the energy and latency improvements as a result of the design choices made available by this protocol. The use of transmission lines as a physical interconnect medium shows promise for deep submicron technologies. In our evaluations, we notice a lower energy footprint, as well as vastly reduced wire latency for transmission line interconnects. We approach this problem from two sides. Using field solvers, we investigate the physical design choices to determine the optimal way to implement these lines for a given back-end-of-line (BEOL) stack. We also approach the problem from a system designer's viewpoint, looking at ways to optimize the lines for different performance targets. This work analyzes the advantages and pitfalls of implementing asynchronous channel protocols for communication over long distances. Finally, the innovations resulting from this work are applied to a network-on-chip design example and the resulting power-performance benefits are reported

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Approximate energy-efficient encoding for serial interfaces

Serial buses are ubiquitous interconnections in embedded computing systems that are used to interface processing elements with peripherals, such as sensors, actuators, and I/O controllers. Despite their limited wiring, as off-chip connections they can account for a significant amount of the total power consumption of a system-on-chip device. Encoding the information sent on these buses is the most intuitive and affordable way to reduce their power contribution; moreover, the encoding can be made even more effective by exploiting the fact that many embedded applications can tolerate intermediate approximations without a significant impact on the final quality of results, thus trading off accuracy for power consumption. We propose a simple yet very effective approximate encoding for reducing dynamic energy in serial buses. Our approach uses differential encoding as a baseline scheme and extends it with bounded approximations to overcome the intrinsic limitations of differential encoding for data with low temporal correlation. We show that the proposed scheme, in addition to yielding extremely compact codecs, is superior to all state-of-the-art approximate serial encodings over a wide set of traces representing data received or sent from/to sensor or actuators

Remote experimental station for engineering education

This thesis provides a distance-learning laboratory for students of electrical and computer engineering department where the instructor can conduct experiments on a computer and send the results to the students at remote computers. The output of the experiment conducted by the instructor is sampled using a successive approximation Analog to Digital (A/D) converter. A microcontroller collects samples using high speed queued serial peripheral interface clock and transmits data to IBM-compatible personal computer over a serial port interface, where the samples are processed using Fast Fourier Transforms and graphed. The client/server application developed transfers the acquired samples over Transmission Control Protocol/Internet Protocol (TCP/IP) network with operational Graphical User Interface (GUI) to the remote computers where the samples are processed and presented to students. The application was tested on all Windows platforms and various Internet speeds (56k modem, Digital Subscriber Line (DSL), Local Area Network (LAN)). The results were analyzed and appropriate methodology of Remote Experimental Station was formulated

Study and simulation of low rate video coding schemes

The semiannual report is included. Topics covered include communication, information science, data compression, remote sensing, color mapped images, robust coding scheme for packet video, recursively indexed differential pulse code modulation, image compression technique for use on token ring networks, and joint source/channel coder design

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design