Design, fabrication and characterization of silicon microlenses for IR-CCD image sensors

There is a growing trend in the study of Focal Plane Arrays(FPAs) of very small microlenses, used for a wide variety of imaging and sensing applications, to increase optical efficiency. Present day sensor technology might take a different direction altogether with the development of compact, high quality, high resolution imaging microlenses, which could make the fill factor \u3e90%. A method to increase light sensitivity of Interline Transfer(IT) type image sensors is to position microlens FPAs on top of the image sensors. FPAs are structures of small lenses which focus the incoming light on the photo sensitive part of the image sensor. The objective of this thesis was to develop reliable and efficient microlens FPAs for a 320 X 244 element PtSi-IT infrared image sensor. The proposed FPAs overcome the difficulty most commonly faced with IT image sensors i.e. low light sensitivity, and in fact makes it superior in light sensitivity to Frame Transfer/Frame Interline Transfer types of image sensors. We have introduced additional degrees of freedom into surface profile of microlens. ZEMAX tool was deployed to model, analyze and assist in the design of the lenses. Standard IC processes were applied to fabricate the lenses with a strict control over process parameters. As a result, we have fabricated prototype microlenses which are expected to assist in obtaining the high sensitivity level of the sensor

Design and characterization of ultra high frame rate burst image sensors

This thesis research was aimed at investigating and designing novel architectures required for ultra high frame rate (UHFR) imagers capable of operating at frame rates in excess of 106 frames/sec. To demonstrate the feasibility of these architectures, a 180 x 180 element UHFR-I imager was designed and fabricated. The imager chip stored the latest 32 frames at its on-chip memory locations rather than performing a continuous readout. It was demonstrated that this architecture approach could achieve a frame acquisition rate of 2 x 106 frames/sec. Additionally, other novel design features were incorporated to minimize optical cross talk and output amplifier noise, and maximize charge handling capacity. Two-dimensional (2-D) process and device simulations were performed to optimize optical cross talk and results compared favorably with experimental data of the fabricated chip. This tested imager was fabricated at the research laboratory of Sarnoff Corporation and had 4-levels of polysilicon, 3-levels of metal, eight implants and 21 photo mask levels. Simulations were also performed to characterize optical cross talk as a function of wavelength, optical shield aperture and epi-substrate doping. The measured value of optical cross talk was at least a factor of 40 times lower and maximum frame rate was a factor of 4 higher than previously published results for very high frame rate (VHFR) imager. The experimental results were used to design a new 64 x 64 element UHFR-II imager with an architecture capable of an image capture rate of 107 frames/sec. This architecture requires only 3-levels of polysilicon and 2-levels of metal and stores the latest 12 frames at its on-chip memory locations. Simulation results indicate that a frame rate of 107 frames/sec can certainly be obtained

CCD image sensor induced error in PIV applications

The readout procedure of charge-coupled device (CCD) cameras is known to generate some image degradation in different scientific imaging fields, especially in astrophysics. In the particular field of particle image velocimetry (PIV), widely extended in the scientific community, the readout procedure of the interline CCD sensor induces a bias in the registered position of particle images. This work proposes simple procedures to predict the magnitude of the associated measurement error. Generally, there are differences in the position bias for the different images of a certain particle at each PIV frame. This leads to a substantial bias error in the PIV velocity measurement (~0.1 pixels). This is the order of magnitude that other typical PIV errors such as peak-locking may reach. Based on modern CCD technology and architecture, this work offers a description of the readout phenomenon and proposes a modeling for the CCD readout bias error magnitude. This bias, in turn, generates a velocity measurement bias error when there is an illumination difference between two successive PIV exposures. The model predictions match the experiments performed with two 12-bit-depth interline CCD cameras (MegaPlus ES 4.0/E incorporating the Kodak KAI-4000M CCD sensor with 4 megapixels). For different cameras, only two constant values are needed to fit the proposed calibration model and predict the error from the readout procedure. Tests by different researchers using different cameras would allow verification of the model, that can be used to optimize acquisition setups. Simple procedures to obtain these two calibration values are also described

Space optical instruments optimisation thanks to CMOS image sensor technology

Today, both CCD and CMOS sensors can be envisaged for nearly all visible sensors and instruments designed for space needs. Indeed, detectors built with both technologies allow excellent electro-optics performances to be reached, the selection of the most adequate device being driven by their functional and technological features and limits. The first part of the paper presents electro-optics characterisation results of CMOS Image Sensors (CIS) built with an optimised CMOS process, demonstrating the large improvements of CIS electro-optics performances. The second part reviews the advantages of CMOS technology for space applications, illustrated by examples of CIS developments performed by EADS Astrium and Supaéro/CIMI for current and short term coming space programs

Charge coupled device image sensor study

An evaluation of a charge-coupled device (CCD) image sensors for use in spacecraft-borne imaging systems was conducted. The study resulted in design recommendations for two sensors, an approximately 500 times 500 element imaging device and a 1 times 190 element linear imaging device with a 190 times 121 buffer store. Emphasis was placed on the higher resolution, area-imaging sensor. The objectives of the proposed sensors are listed, results of the experiments are analyzed, and estimates of the device performance are presented. A summary of the major technical recommendations is included

A Low-Power Capacitive Transimpedance D/A Converter

This thesis proposes a new low-power and low-area DAC for single-slope ADCs used in CMOS image sensors. With increase in resolution requirements for ADCs, conventional DAC architectures suffered the limitation of either large area or high power consumption with higher resolution scaling. Thus, the proposed capacitive transimpedance amplifier DAC (CTIA DAC) could solve this by offering the resolution requirement required without taking a hit on the area or power budget. The thesis has been structured in the following manner: The first chapter introduces image sensors in general and talks about progression through different image sensors and pixel architectures that have been used through the years. It also explains the operation of a CMOS image sensor from a paper published from Sony on high-speed image sensors. The second chapter presents the importance and role of DACs in CMOS image sensors and briefly explains a few commonly used DAC architectures in image sensors. It explains the advantages and disadvantages of present architectures and leads the discussion towards the development of the proposed DAC. The third chapter gives an overview of the CTIA DAC and explains the working of the different circuit blocks that are used to implement the proposed DAC. Chapter Four explains the design approach for the blocks explained in Chapter Three. It presents the critical design choices that were made for overall performance of the DAC. Results of individual blocks and the DAC as a whole are presented and compared against other recently published DAC papers. The final chapter summarizes some key results of the design and talks about the scope for future work and improvement

Technical guidance for the development of a solid state image sensor for human low vision image warping

This report surveys different technologies and approaches to realize sensors for image warping. The goal is to study the feasibility, technical aspects, and limitations of making an electronic camera with special geometries which implements certain transformations for image warping. This work was inspired by the research done by Dr. Juday at NASA Johnson Space Center on image warping. The study has looked into different solid-state technologies to fabricate image sensors. It is found that among the available technologies, CMOS is preferred over CCD technology. CMOS provides more flexibility to design different functions into the sensor, is more widely available, and is a lower cost solution. By using an architecture with row and column decoders one has the added flexibility of addressing the pixels at random, or read out only part of the image

Charge-coupled-device parallel-to-serial converter

A CCD parallel-to-serial converter comprising two successions of charge transfer stages, recurrently side-loaded with respective ones of parallelly supplied charge packets, then serially unloaded by time-interleaved respective shift register operations. The charge packets converted to time-division-multiplexed serial form are supplied to a shared electrometer, and the electrometer response is de-multiplexed. Preferably, shift register operations are carried forward concurrently at the same rate, but with the final charge transfer stages clocked in phases staggered in time