Capacitive Microaccelerometers And Fabrication Methods

Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (17 pF/g). Themicrostructures are fabricated in thick(> 100 µm) siliconon-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (> 10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is -91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/√Hz). The IC consumes 6 mW power and measures 0.65 mm2 core area.Georgia Tech Research Corporatio

A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 mu M CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025 x 515 mm(2) and is marked by a power consuption of 84 mu W. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/degrees C

New Electronic Interface Circuits for Humidity Measurement Based on the Current Processing Technique

The paper describes a new electronic conditioning circuit based on the current-processing technique for accurate and reliable humidity measurement, without post-processing requirements. Pseudobrookite nanocrystalline (Fe2TiO5) thick film was used as capacitive humidity transducer in the proposed design. The interface integrated circuit was realized in TSMC 0.18 mu m CMOS technology, but commercial devices were used for practical realization. The sensing principle of the sensor was obtained by converting the information on environment humidity into a frequency variable square-wave electric current signal. The proposed solution features high linearity, insensitivity to temperature, as well as low power consumption. The sensor has a linear function with relative humidity in the range of Relative Humidity (RH) 30-90 %, error below 1.5 %, and sensitivity 8.3 x 10(14) Hz/F evaluated over the full range of changes. A fast recovery without the need of any refreshing methods was observed with a change in RH. The total power dissipation of readout circuitry was 1 mW

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

A Fully Differential CMOS Potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200μm×200μm prototype was fabricated in a standard 0.35μm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-tofrequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments

A CMOS Analog Front-End for Tunnelling Magnetoresistive Spintronic Sensing Systems

This paper presents a CMOS readout circuit for an integrated and highly-sensitive tunnel-magnetoresistive (TMR) sensor. Based on the characterization of the TMR sensor in the finite-element simulation, using COMSOL Multiphysics, the circuit including a Wheatstone bridge and an analogue front-end (AFE) circuit, were designed to achieve low-noise and low-power sensing. We present a transimpedance amplifier (TIA) that biases and amplifies a TMR sensor array using switched-capacitors external noise filtering and allows the integration of TMR sensors on CMOS without decreasing the measurement resolution. Designed using TSMC 0.18 μm 1V technology, the amplifier consumes 160 nA at 1.8 V supply to achieve a dc gain of 118 dB and a bandwidth of 3.8 MHz. The results confirm that the full system is able to detect the magnetic field in the pico-Tesla range with low circuit noise (2.297 pA/√Hz) and low power consumption (86 μW). A concurrent reduction in the power consumption and attenuation of noise in TMR sensors makes them suitable for long-term deployment in spintronic sensing systems

Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers

In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g∼389 mV/g, the output nonlinearity of 0.43% FSO∼0.60% FSO, the input range of ±2 g and a bias instability of 122 μg∼229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be 74.00 dB∼75.23 dB and 180 μg/rtHz∼190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%∼1.9% and 0.3%∼0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics