Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

Improved Decoding of Staircase Codes: The Soft-aided Bit-marking (SABM) Algorithm

Staircase codes (SCCs) are typically decoded using iterative bounded-distance decoding (BDD) and hard decisions. In this paper, a novel decoding algorithm is proposed, which partially uses soft information from the channel. The proposed algorithm is based on marking certain number of highly reliable and highly unreliable bits. These marked bits are used to improve the miscorrection-detection capability of the SCC decoder and the error-correcting capability of BDD. For SCCs with $2$-error-correcting Bose-Chaudhuri-Hocquenghem component codes, our algorithm improves upon standard SCC decoding by up to $0.30$~dB at a bit-error rate (BER) of $10^{-7}$. The proposed algorithm is shown to achieve almost half of the gain achievable by an idealized decoder with this structure. A complexity analysis based on the number of additional calls to the component BDD decoder shows that the relative complexity increase is only around $4\%$ at a BER of $10^{-4}$. This additional complexity is shown to decrease as the channel quality improves. Our algorithm is also extended (with minor modifications) to product codes. The simulation results show that in this case, the algorithm offers gains of up to $0.44$~dB at a BER of $10^{-8}$.Comment: 10 pages, 12 figure

Artificial Intelligence Aided Receiver Design for Wireless Communication Systems

Physical layer (PHY) design in the wireless communication field realizes gratifying achievements in the past few decades, especially in the emerging cellular communication systems starting from the first generation to the fifth generation (5G). With the gradual increase in technical requirements of large data processing and end-to-end system optimization, introducing artificial intelligence (AI) in PHY design has cautiously become a trend. A deep neural network (DNN), one of the population techniques of AI, enables the utilization of its ‘learnable’ feature to handle big data and establish a global system model. In this thesis, we exploited this characteristic of DNN as powerful assistance to implement two receiver designs in two different use-cases. We considered a DNN-based joint baseband demodulator and channel decoder (DeModCoder), and a DNN-based joint equalizer, baseband demodulator, and channel decoder (DeTecModCoder) in two single operational blocks, respectively. The multi-label classification (MLC) scheme was equipped to the output of conducted DNN model and hence yielded lower computational complexity than the multiple output classification (MOC) manner. The functional DNN model can be trained offline over a wide range of SNR values under different types of noises, channel fading, etc., and deployed in the real-time application; therefore, the demands of estimation of noise variance and statistical information of underlying noise can be avoided. The simulation performances indicated that compared to the corresponding conventional receiver signal processing schemes, the proposed AI-aided receiver designs have achieved the same bit error rate (BER) with around 3 dB lower SNR

On hard-decision forward error correction with application to high-throughput fiber-optic communications

The advent of the Internet not only changed the communication methods significantly, but also the life-style of the human beings. The number of Internet users has grown exponentially in the last decade, and the number of users exceeded 3.4 billion in 2016. Fiber links serve as the Internet backbone, hence, the fast grow of the Internet network and the sheer of new applications is highly driven by advances in optical communications. The emergence of coherent optical systems has led to a more efficient use of the available spectrum compared to traditional on-off keying transmission, and has made it possible to increase the supported data rates. To achieve high spectral efficiencies and improve the transmission reach, coding in combination with a higher order modulation, a scheme known as coded modulation (CM), has become indispensable in fiber-optic communications. In the recent years, graph-based codes such as low-density parity-check codes and soft decision decoding (SDD) have been adopted for long-haul coherent optical systems. SDD yields very high net coding gains but at the expense of a relatively high decoding complexity, which brings implementation challenges at very high data rates. Hard decision decoding (HDD) is an appealing alternative that reduces the decoding complexity. This motivates the focus of this thesis on forward error correction (FEC) with HDD for high-throughput, low power fiber-optic communications.In this thesis, we start by studying the performance bounds of HDD. In particular, we derive achievable information rates (AIRs) for CM with HDD for both bit-wise and symbol-wise decoding, and show that bit-wise HDD yields significantly higher AIRs. We also design nonbinary staircase codes using density evolution. Finite length simulation results of binary and nonbinary staircase codes corroborate the conclusions arising from the AIR analysis, i.e., for HDD binary codes are preferable. Then, we consider probabilistic shaping. In particular, we extend the probabilistic amplitude shaping (PAS) scheme recently introduced by B\uf6cherer et al. to HDD based on staircase codes. Finally, we focus on new decoding algorithms for product-like codes to close the gap between HDD and SDD, while keeping the decoding complexity low. In particular, we propose three novel decoding algorithms for product-like codes based on assisting the HDD with some level of soft information. The proposed algorithms provide a clear performance-complexity tradeoff. In particular, we show that up to roughly half of the gap between SDD and HDD can be closed with limited complexity increase with respect to HDD

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Digital VLSI Architectures for Advanced Channel Decoders

Error-correcting codes are strongly adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probes. New and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. This work aims to focus on Polar codes, which are a recent class of channel codes with the proven ability to reduce decoding error probability arbitrarily small as the block-length is increased, provided that the code rate is less than the capacity of the channel. This property and the recursive code-construction of this algorithms attracted wide interest from the communications community. Hardware architectures with reduced complexity can efficiently implement a polar codes decoder using either successive cancellation approximation or belief propagation algorithms. The latter offers higher throughput at high signal-to-noise ratio thanks to the inherently parallel decision-making capability of such decoder type. A new analysis on belief propagation scheduling algorithms for polar codes and on interconnection structure of the decoding trellis not covered in literature is also presented. It allowed to achieve an hardware implementation that increase the maximum information throughput under belief propagation decoding while also minimizing the implementation complexity