Analysis and design of a high frequency induction-heating system

Includes bibliographical references.Advances in power electronic semiconductor technology are making high frequency converters for induction heating more feasible at power levels up to 50kW. This research presents the development and analysis of a solid-state induction-heating system, operating directly off single-phase mains frequency, which enables optimum and efficient operation over a frequency range of 80kHz to 200kHz. The system essentially comprises a DC-DC converter configured as a controlled current source, which feeds a load resonant DC-AC inverter, driving a parallel resonant load circuit. The load circuit comprises an induction-heating coil and a reactive power compensating capacitor. The systems active switching elements comprise power MOSFET's but can be extended to almost any other controlled power devices such as IGBT's, BJT's, SCR's, GTO's or SIT's. An automatic frequency control system ensures that the DC-AC inverter drives the load at its resonant frequency, thereby achieving zero voltage switching of the power semiconductors. This operating mode always ensures maximum power transfer to the load as well as maximum operating efficiency of the DC-AC inverter. Driving the load at resonance presents an essentially resistive load to the DC-DC converter, thereby reducing the losses associated with a reactive load. A compact circuit layout combined with this optimum mode of operation eliminates the need for any snubber circuit components in both the DC-DC and DC-AC converters at this power level. An overview into various applications and technologies of induction-heating is presented in this research. A detailed analysis of the induction-heating coil and work- piece are presented in order to aid the design of the load circuit. The induction-heating technology overview presents various induction-heating power sources, discussing the configurations of various topologies. A brief mathematical analysis is used to describe the operation of power electronic converters employed in the induction-heating system developed for this research. The parallel resonant induction-heating load circuit is characterised mathematically, allowing for the determination of the optimum operating conditions. This is followed by a simulation analysis, which is used to gain insight into the problem of frequency control. The frequency control system is modelled and the steady-state error response evaluated under different input conditions. Experimental results on the system implemented, based on operating waveforms and efficiency measurements of the solid-state induction-heating system are presented along with recommendations for future work. The implemented power source was tested at a maximum power of 2.3kW at 151kHz. A system efficiency of 86% at 1.3kW was measured when operating at 138kHz. This design however, provides for scaling to power levels up to 50kW. The induction-heating system's frequency tracking capability is evaluated by heating a steel work-piece through its Curie transition temperature. The induction-heating system is used to heat a 26mm x 35mm stainless-steel billet (work-piece) to 1200°C in 130 seconds using the calculated power of 1.35kW

Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability

An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development

Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

Hot electron currents in MOSFETs.

Silicon has become the material of choice for fabrication of high circuit density, low defect density and high speed integration devices. CMOS technology has been favoured as an attractive candidate to take advantage of the performance enhancements available through miniturisation. However, hot carrier effects in general, and hot electron currents in particular, are posing as the main obstacle to a new era of sub-micron architecture in semiconductor device technology. Electron transport in modern sub-micron device is often governed by mechanisms that were not relevant to long-channel devices. Many of the classical device models are based upon such convenient assumptions as "thermal equilibrium" and "uniform local electric field". With the downscaling of devices, hot electron currents are becoming increasingly inherent. These currents arise from the fact that electrical fields in small geometry devices can reach very high values and can vary rapidly in space. The large electric field can Impart significant kinetic energies to the carriers. In thermal equilibrium, all elementary excitations in a semiconductor (eg. Electrons, holes, phonons) can be characterised by a temperature that is the same as the lattice temperature. Under the influence of large electric fields, however, the distribution function of these elementally excitations deviate from those in thermal equilibrium. The term "Hot Carriers" is often used to describe these non-equilibrium situations. In this thesis hot electron currents, in particular their physical origins and dependence upon various operational and geometrical parameters, have been discussed and then quantified in a number of models based on the "Lucky Drift" theory of transport. Temperature is then used as a tool to differentiate between the underlying physical processes, and to determine if reliability problems related to hot electron effects would improve under cryogenic operation. It has been the prime objective of this work from the outset to concentrate on the study of N-channel devices. This is primarily due to the fact that N-channel MOSFET's are more prone to hot electron effects, and therefore, studies in the nature of this enhanced susceptibility could prove to be more fruitful

Evaluation of two prototype three phase photovoltaic water pumping systems

Bibliography: p. 221-223.Two prototype three phase AC photovoltaic pump systems (Solvo, ML T) and a DC PV pump (Miltek) were tested on a farm borehole in Namibia (latitude 21°6', longitude 17°6'). The PV array consisted of twelve modules (636Wpeak) mounted on a single-axis passive tracker. The depth of the water was 75m and a progressive cavity pump with a self-compensating stator was used in all the tests. Customised data acquisition was designed to measure performance characteristics through a range of operating conditions (mainly steady state); a secondary data acquisition system was used to capture samples of high frequency signals. The data allowed detailed analysis of system, subsystem and component performance, as well as performance evaluation over Standard Solar Days. The focus of the investigation was evaluation of the AC prototypes, in terms of performance, other technical factors, reliability and economic criteria. The analog-based DC system served as a basis for comparison. Both AC systems employed microprocessor control and PWM variable-frequency variable-voltage inversion. Efficiencies, optimality, stability, start-up behaviour, non-productive operating modes and protection were examined. A number of recommendations were proposed for improvements in the basic control algorithms, monitoring and managing non-productive modes, improved protection, layout and user diagnostic features