Robust high-accuracy high-speed continuous-time CMOS current comparator

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date

A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V

Design of pixel-level ADCs for energy-sensitive hybrid pixel detectors

Single-photon counting hybrid pixel detectors have shown\ud to be a valid alternative to other types of X-ray imaging\ud devices due to their high sensitivity, low noise, linear behavior\ud and wide dynamic range. One important advantage of these\ud devices is the fact that detector and readout electronics are\ud manufactured separately. This allows the use of industrial\ud state-of-the-art CMOS processes to make the readout\ud electronics, combined with a free choice of detector material\ud (high resistivity Silicon, GaAs or other). By measuring not\ud only the number of X-ray photons but also their energies (or\ud wavelengths), the information content of the image increases,\ud given the same X-ray dose. We have studied several\ud possibilities of adding energy sensitivity to the single photon\ud counting capability of hybrid pixel detectors, by means of\ud pixel-level analog-to-digital converters. We show the results of\ud simulating different kinds of analog-to-digital converters in\ud terms of power, area and speed

Design and Analysis of High Gain Low Power CMOS Comparator

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V

Switched Current Sigma-Delta Modulator with a New Comparator Structure Designed Based on VHDL-AMS Description

The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. The prototype VHDL-AMS description, with the help of elaborated EDA tools, is automatically translated into the SI realization. Another tool helps the designer to create the layout. The paper also describes a new current mode comparator, which is used in the design. Postlayout simulation results are presented