Single-photon counting hybrid pixel detectors have shown\ud
to be a valid alternative to other types of X-ray imaging\ud
devices due to their high sensitivity, low noise, linear behavior\ud
and wide dynamic range. One important advantage of these\ud
devices is the fact that detector and readout electronics are\ud
manufactured separately. This allows the use of industrial\ud
state-of-the-art CMOS processes to make the readout\ud
electronics, combined with a free choice of detector material\ud
(high resistivity Silicon, GaAs or other). By measuring not\ud
only the number of X-ray photons but also their energies (or\ud
wavelengths), the information content of the image increases,\ud
given the same X-ray dose. We have studied several\ud
possibilities of adding energy sensitivity to the single photon\ud
counting capability of hybrid pixel detectors, by means of\ud
pixel-level analog-to-digital converters. We show the results of\ud
simulating different kinds of analog-to-digital converters in\ud
terms of power, area and speed

Nauta, Bram

San Segundo Bello, David

Visschers, Jan

English

Single-photon counting hybrid pixel detectors have shown to be a valid alternative to other types of X-ray imaging devices due to their high sensitivity, low noise, linear behavior and wide dynamic range. One important advantage of these devices is the fact that detector and readout electronics are manufactured separately. This allows the use of industrial state-of-the-art CMOS processes to make the readout electronics, combined with a free choice of detector material (high resistivity Silicon, GaAs or other). By measuring not only the number of X-ray photons but also their energies (or wavelengths), the information content of the image increases, given the same X-ray dose. We have studied several possibilities of adding energy sensitivity to the single photon counting capability of hybrid pixel detectors, by means of pixel-level analog-to-digital converters. We show the results of simulating different kinds of analog-to-digital converters in terms of power, area and speed

San Segundo Bello, D.

University of Twente Research Information

Design of Pixel-Level ADCs for Energy-Sensitive Hybrid Pixel DetectorsDavid San Segundo Bello1,2, Bram Nauta2, Jan Visschers11NIKHEF, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands2ICD-group, MESA+ Research Institute, University of Twente, P.O.Box 217  7500 AE Enschede, The NetherlandsAbstractSingle-photon counting hybrid pixel detectors have shownto be a valid alternative to other types of X-ray imagingdevices due to their high sensitivity, low noise, linear behaviorand wide dynamic range. One important advantage of thesedevices is the fact that detector and readout electronics aremanufactured separately. This allows the use of industrialstate-of-the-art CMOS processes to make the readoutelectronics, combined with a free choice of detector material(high resistivity Silicon, GaAs or other). By measuring notonly the number of X-ray photons but also their energies (orwavelengths), the information content of the image increases,given the same X-ray dose. We have studied severalpossibilities of adding energy sensitivity to the single photoncounting capability of hybrid pixel detectors, by means ofpixel-level analog-to-digital converters. We show the results ofsimulating different kinds of analog-to-digital converters interms of power, area and speed.I.  INTRODUCTIONSemiconductor pixel detectors are now widely used inhigh-energy physics experiments [1],[2]. Their application asphoton counting devices for X-ray and gamma-ray detectionhas also been demonstrated [3],[4].A detailed explanation of the principle and functionality ofpixel detectors can be found elsewhere [5]. The basicdifferences with other imaging detectors (such as CCDs,CMOS imagers, film, phosphor plates, etc…) are directconversion and individual photon detection. Direct conversionmeans that the photon deposits an amount of charge in thedetector directly proportional to the energy of the photon. Thischarge is then processed by the readout electronics. Individualphoton detection refers to the fact that photons are detectedindividually one by one in each pixel, and thus no chargeintegration is taking place, as is the case in almost all otherimaging detectors.In hybrid pixel detectors, the detector and the readoutelectronics are manufactured independently and they areconnected afterwards using flip-chip bonding techniques. Thisallows for separate optimization of the detector and the readoutelectronics.A review of the design and assembly issues of pixeldetectors for use in biomedicine and high energy physics canbe found in [6].In X-ray imaging, the detection and measurement of theenergy of individual X-ray photons can improve the finalimage given the same X-ray dose used in integrating or photoncounting techniques.The individual photon detection performed in pixeldetectors allows the addition of pixel-level energy sensitivityby adding circuitry that converts, stores and sends off-chip theenergy information. The conversion can be performed usinganalog-to-digital converters (ADCs) in the pixel electronics.The use of ADCs at the pixel level has also been shown toimprove the spatial resolution in particle detection applications[7].We will start by introducing the pixel architecture that willbe the basis for our design. Then, we will explain the differentADC structures we have studied. Finally, we will mention thefuture work we intend to do and the conclusions that can bedrawn from the work done so far.II.  PIXEL ARCHITECTUREWe assume that the pixel electronics have a structure suchas the one shown in figure 1. The signal deposited in thedetector by each individual photon is first amplified andintegrated (for example, using a charge sensitive amplifier[8]). This is needed in order to convert the deposited charge toa voltage or current that can be converted by the ADC, andalso to increase the signal-to-noise ratio. At the same time, apulse is generated if the signal is above the noise level. Wewill not study this block in this paper.Figure 1: Block diagram of the pixel architectureThe analog signal and the digital pulse coming out of thisfirst block are the inputs to the analog to digital converter. Thepulse is used to start the conversion, and the output of theamplifier is the signal that will be converted.After the ADC, a fast digital readout circuit is needed inorder to allow a new photon hit to be processed in the pixel. Inmost pixel readout chips there is a clear distinction betweenthe image acquisition and the data readout. In our case,however, the digital readout has to be working while an imageis being acquired, as we do not intend to provide means forstoring more than one hit in the pixel. This means that an eventby event readout is needed for this kind of circuit. Thecircuitry needed to perform this readout will not be explainedin this paper.III.  ANALOG TO DIGITAL CONVERTERSA.  Noise considerationsAs we have seen in the previous section, a relatively largeamount of digital circuit activity will be happening at the sametime the amplification and the conversion are taking place.This is not the case in most pixel readout chips, where thedifferent time slots for image acquisition and data readoutdivide clearly the analog processing and the digital activitybetween the two processes.This means that, for the ADC, the effects of electronicdevice noise will be less important than the noise generated bythe digital activity. Noise from power supply coupling,crosstalk, substrate fluctuations and stray carriers are likely tobe well above the thermal, shot and flicker noise associatedwith silicon devices [9].B.  SpecificationsOur goal in studying different ADC structures is to find outthe trade-offs that each architecture offers. The differentapplications where an energy sensitive pixel detector readoutchip would be used have different requirements in terms ofpixel area and photon rate.As our first goal, we will design 4-bit ADCs, as thiscorresponds approximately to the best resolution that can beachieved with a room temperature GaAs detector [10].The area for the pixel (including amplifier, ADC andreadout) should not exceed 100• m by 100• m. Assuming atypical active imaging area of 1 cm by 1 cm, we end up withapproximately 10000 pixels.In order to calculate a typical conversion rate, we assume aphoton rate of 106 photons per second and per squaremillimetre. This is the typical rate for radiologicalapplications. With this photon rate and a pixel size of 100• mby 100• m we get a photon rate per pixel of 104 photons persecond. Taking a conservative approach (as we have to add theintegration and readout time), we will use a conversion time ofapproximately 1 • s. This time is also comparable to thecounting frequency in photon counting pixel detectors [3].The power consumption of the ADC should be minimal.Assuming that the power consumed by all the ADCs isapproximately 100 mW, and supposing a number of 10000pixels, we will take a typical power consumption of 10 • W perpixel. In order to be able to compare the performance of thedifferent ADCs we choose a first value of full-scale currentequal to 1• A.All the designs are being done in a 0.25• m CMOS digitalprocess with 6 metal layers. We used a current-mode approachfor all the designs reported in this paper.C.  Flash ADCA flash analog-to-digital converter is probably the fastest,but its cost in area and power consumption can be tooprohibitive if we want to have several hundreds of these ADCsin the same chip. However, by working in the current-modedomain, we can reduce significantly the power and arearequirements.In our case, we use a current-mode comparator based onthe one described in [11]. We can see the principle of thecomparator in Figure 2.Figure 2: Schematic view of the current-mode comparatorThe basic circuit consists of an inverting amplifier and afeedback consisting of an NMOS transistor and a PMOStransistor. The NMOS transistor is connected from VDD to theinput of the amplifier with its gate controlled by the amplifieroutput, and the PMOS transistor is connected between theinput of the amplifier and ground with its gate also controlledby the output of the amplifier.Figure 3 shows the simulated input/output characteristic ofthe ADC with a 1 µs conversion time.01234567891011121314150 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9input current (µA)output digital codeSimulatedidealFigure 3: I/O characteristic of the Flash analog-to-digital converterThe following table summarizes some of the specificationsof the flash ADC.Table 1Characteristics of the flash ADCCharacteristic Value UnitsFull scale 1 $Resolution 4 bitsPower supply 1.8 VStatic power consumption 18 :Area 70 x 70 P2D.  Successive Approximation ADCThe converter explained in the previous section is fast, butthe power consumption is relatively high. We can think oftrading some speed for power and use a successiveapproximation type of converter. Figure 4 shows a blockdiagram of such a converter.Figure 4: Block diagram of the successive approximaation ADCThis converter needs a number of clock cycles equal to thenumber of bits in order to perform the conversion. We use acurrent-mode binary-weighted DAC, and the comparator is thesame type as the one used in the flash converter. Thecomplexity of the circuit lies mostly in the digital circuitry, asit is responsible for switching ON and OFF the current sourcesin the DAC in response to changes in the comparator output.Figure 5 shows the layout of this converter.Figure 5: Layout of the successive approximation analog-to-digitalconverterIn the left side the DAC and the comparator can be seen,while the digital circuitry is located on the right. It can beclearly seen that the digital circuitry takes more than half thetotal area of the converter. In this first prototype, the logic wasdesigned using conventional CMOS logic.Figure 6 shows the input/output characteristic of such aconverter working at a 1 µs conversion time.01234567891011121314150 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9Input current (µA)Output digital codeSimulatedIdealFigure 6: I/O characteristic of the successive approximation analog-to-digital converterThe speed of the comparator used is proportional to thedifference of currents applied to its input. This means that byincreasing the full scale current (and hence the ILSB value) wecould achieve higher conversion speeds at the price of a higherpower consumption. This would translate to a lower offset inthe I/O characteristic.The following table summarizes the characteristics of thisconverter.Table 2Characteristics of the successive approximation ADCCharacteristic Value UnitsFull scale 1 $Resolution 4 bitsPower supply 1.8 VStatic power consumption 3.8 :Area 90 x 70 P2E.  Algorithmic-pipelinedThe problem with the previous two types of converters isthe need for a relatively complex digital circuitry in the pixel.This can lead to crosstalk as well as substrate coupling noiseproblems. We can also think of moving some (of all) theprocessing done in the digital domain to the analog domain.A converter that does such a thing is the current-modealgorithmic ADC, as described in [12]. The basic buildingblock of this converter can be seen in Figure 7.Figure 7: Block diagram of the basic building block for thealgorithmic analog-to-digital converterIn Figure 7, the input signal is multiplied by 2 andcompared with a reference value equal to the full-scale currentof the converter. If the reference is higher, the analog output isset equal to the input multiplied by two, and the digital outputis set low. If the reference is lower, the analog output is setequal to the input multiplied by two minus the reference, andthe digital output is set high.By connecting N such blocks one after the other, we canobtain an N-bit ADC, as Figure 8 shows for a 4-bit case.Figure 8: Block diagram of an algorithmic-pipelined analog-to-digitalconverterThe simulated input/output characteristic of the ADC witha conversion time of 1 µscan be seen in Figure 9.01234567891011121314150 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1Input current (µ A)Digital output codeSimulatedIdealFigure 9: I/O characteristic of an algorithmic-pipelined ADCThe characteristics of the ADC can be seen in thefollowing table.Table 3Characteristics of the algorithmic ADCCharacteristic Value UnitsFull scale 1 $Resolution 4 bitsPower supply 1.8 VStatic power consumption 9.8 :Area 80x80 P2IV.  FUTURE WORKAt the end of this year, it is expected to submit a test chipwith arrays of these ADC structures in order to test theirfunctionality. Once the circuits have been measured andcharacterized, a study of how to perform a fast readout of thedigital values has to be performed in order to be able to build afirst working prototype.Additionally, ways to improve the conversion speed whilekeeping the same power consumption and occupied area mustbe studied deeper.V.  CONCLUSIONSWe have shown that it is possible to add analog to digitalconverters at pixel level in pixel detector readout chips. Interms of power and occupied area, all three architecturesstudied so far fall inside the requirements. The biggestdifferences between them are in the digital circuitry needed toperform the conversion and in the speed/linearity relationship.It is clear that a faster current comparator would allow forfaster ADCs, but the power requirements for the system mustbe taken into account.VI.  ACKNOWLEDGMENTSThis work is partly funded by the European Union undergrant number TMR ERBFMRXCT980196.VII.  REFERENCES[1] ATLAS collaboration, "ATLAS Pixel Detector: TechnicalDesign Report", CERN-LHCC-98-013, 31 May 1998[2] ALICE collaboration, "ALICE: Technical Design Reportof the Inner Tracking System (ITS)", CERN-LHCC-99-012, 18 June 1999[3] M. Campbell, E.H.M. Heijne, G. Meddeler, E. Pernigotti,W. Snoeys, ’’Readout for a 64 x 64 Pixel Matrix with 15-bit Single Photon Counting", IEEE Transactions onNuclear Science, vol. 45 (3), 751-753, June 1998.[4] P. Fischer, J. Hausmann, M. Overdick, B. Raith, N.Wermes, L. Blanquart, V. Bonzom, P. Delpierre, "Acounting pixel readout chip for imaging applications",Nuclear Instruments and Methods in Physics Research A,volume 405, pp. 53-59, 1998[5] B. Mikulec, "Single Photon Detection with SemiconductorPixel Arrays for Medical Imaging Applications", CERN20 Jun 2000. Thesis: Univ. Vienna 2000. Available fordownload fromhttp://documents.cern.ch/archive/electronic/cern/preprints/thesis/thesis-2000-021.pdf[6] M. Caria, "Current trends on design and assembly of pixeldetector systems in biomedicine and high-energy physics",Nuclear Instruments and Methods in Physics Research A,volume 447, pp. 167-177, 2000[7] D.C. Christian, J.A. Appel, G. Cancelo, S. Kwan, J. Hoff,A. Mekkaoui, J. Srage, R. Yarema, S. Zimmermann,’’Development of a pixel readout chip for BTeV’’, NuclearInstruments and Methods in Physics Research A, volume435, pp. 144-152, 1999[8] Glenn F. Knoll, "Radiation detection and measurement"3rd ed, Wiley New York, 2000[9] T. Schmerbeck, "Noise coupling in mixed-mode ICs",CMOS and BiCMOS IC design 2000, LausanneSwitzerland 4-8 September 2000[10] E. Bertolucci, M. Conti, G. Mettivier, P. Russo, A. Cola,F. Quaranta, L. Vasanelli, M. G. Bisogni, U. Bottigli, M.E. Fantacci, A. Stefanini, "Spectroscopic performance ofsemi-insulating GaAs detectors for digital radiography",Nuclear Instruments and Methods in Physics Research A,volume 422, pp. 247-251 (1999)[11] H. Träff, "Novel approach to high speed CMOS currentcomparators", Electronics Letters, volume 28, number 3,pp. 310-312, January 1992[12] D.G. Nairn and A.T. Salana, ''Current-mode algorithmicanalog-to-digital converters'', IEEE Journal of Solid-StateCircuits, vol. 25, no.4, pp. 997-1003, august 1990

Design of pixel-level ADCs for energy-sensitive hybrid pixel detectors

NARCIS 

A counting pixel readout chip for imaging applications&quot;,

ALICE: Technical Design Report of the Inner Tracking System (ITS)&quot;,

ATLAS Pixel Detector: Technical Design Report&quot;,

Current trends on design and assembly of pixel detector systems in biomedicine and high-energy physics&quot;, Nuclear Instruments and Methods in

Current-mode algorithmic analog-to-digital converters'',

Noise coupling in mixed-mode ICs&quot;,

Novel approach to high speed CMOS current comparators&quot;,

Radiation detection and measurement&quot; 3rd ed,

Readout for a 64 x 64 Pixel Matrix with 15-bit Single Photon Counting&quot;,

Single Photon Detection with Semiconductor Pixel Arrays for Medical Imaging Applications&quot;,

Spectroscopic performance of semi-insulating GaAs detectors for digital radiography&quot;,

Design of pixel-level ADCs for energy-sensitive hybrid pixel detectors

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