BCD To Floating Point Converter With Floating Point Adder Unit Using VHDL

To perform numerical calculations on modern computers floating point arithmetic is a better way of approximating real number arithmetic. Its advantage is that it can support a much wider range of values rather than fixed point and integer representation. Addition/Subtraction, Multiplication and division are the common arithmetic operations. Among them the most complex one is the floating point addition. Adder is the most important element of complex arithmetic circuits, in which input should be given in standard IEEE754 format. The main objective of the work is to design and implement a binary to IEEE 754 floating point converter to represent 32 bit single precision floating point values. Then the converter will be placed at the input of the designed floating point adder module to improve the overall design. The modules are written using very high speed integrated circuit (VHSIC) Hardware Description Language (VHDL), and are then synthesized for Xilinx vertex E FPGA using Xilinx Integrated Software Environment(ISE) design suite 13.1. DOI: 10.17762/ijritcc2321-8169.150710

A study of high-speed AD and DA converters using redundancy techniques Interim report, May 10, 1963 - May 9, 1964

High speed analog-to-digital converters compared using redundancy encoding technique

Household technology acceptance heterogeneity in computer adoption

Technology policy analysis and implementation relies on knowledge and understanding of the "adoption gap" in information technologies among different groups of consumers. Factors that explain the residential "digital divide" also need to be identified and quantified. Through the application of survey data we provide an enhanced understanding of the key factors involved in the choice of residential computer adoption. These choices are analysed using a discrete choice model that reveals that sociodemographic factors strongly influence the adoption of the residential computer. Moreover, we apply the basic findings of the Technology Adoption Model (TAM) into the discrete choice framework heteroscedastically to deepen our understanding of why some households choose not to have computers; above and beyond what may be explained by socio-demography alone. Generally, we find that computer adoption is sensitive to household digital division measures and that the model fit improves with the heteroscedastic addition of the TAM factors. These findings are important for market planners and policymakers who wish to understand and quantify the impact of these factors on the digital divide across different household types, as defined by the TAM model

Progress of analog-hybrid computation

Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging technique

Arithmetic Operations in Multi-Valued Logic

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.Comment: 12 Pages, VLSICS Journal 201