Indirect interconnection networks for high performance routers/switches

Routers form the backbone of the Internet; their kernel, structure, andconfiguration (scheduler) of the backplane (or switching fabrics) dominate the routers’performance, scalability, reliability and cost. As higher performance is required with therapid development of the network applications, router’s architecture has also evolvedfrom the shared backplane to switched backplane, which mainly uses the indirectinterconnection networks.The indirect interconnection networks include crossbar, MIN (multistageinterconnection networks) and some other irregular topologies. At present, most oftoday’s routers and switches are implemented on single crossbar with symmetric bufferarchitecture. In the first part of this dissertation, we introduce novel asymmetric bufferarchitecture for the crossbar in which a new port and a local shared bus are added. Wethen evaluate its performance and simulate under different bus arbitration and buffermanagement algorithms. Our studies indicate that we can get great improvement for thethroughput and low drop rate. Thus we could save a lot of expensive link bandwidth anddecrease the probability of congestion for the network.Single crossbar complexity increases at O(N2) in terms of crosspoint number,which become unacceptable for scalability as the port number (N) increases. A delta classself-routing MIN with complexity of O(N×log2N) has been widely used in the ATMswitches. But the reduction of crosspoint number results in considerable internal blocking.A number of scalable methods have been proposed to solve this problem. One of themuses more stages with recirculation architecture to reroute the deflected packets, whichgreatly increase the latency. In the second part of this dissertation, we propose aninterleaved multistage switching fabrics architecture and assess its throughput with ananalytical model and simulations. We compare this novel scheme with some previousparallel architectures and show its benefits. From extensive simulations under differenttraffic patterns and fault models, our interleaved architecture achieves better performancethan its counterpart of single panel fabric. Our interleaved scheme achieves speedups(over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns,respectively at maximum load (p=1). Moreover, the interleaved fabrics show greattolerance against internal hardware failures

The Open Network Laboratory (a resource for high performance networking research)

The Open Network Laboratory (ONL) is a remotely accessible network testbed designed to enable network researchers to conduct experiments using high performance routers and applications. ONL™s Remote Laboratory Interface (RLI) allows users to easily configure a network topology, initialize and modify the routers™ routing tables, packet classification tables and queuing parameters. It also enables users to add software plugins to the embedded processors available at each of the routers™ ports, enabling the introduction of new functionality. The routers provide a large number of built-in counters to track various aspects of system usage, and the RLI software makes these available through easy-to-use real-time charts. This allows researchers to expose what is happening fiunder the surfacefl enabling them to develop the insights needed to understand system behavior in complex situations and to deliver compelling demonstrations of their ideas in a realistic operating environment. This paper provides an overview of ONL, emphasizing how it can be used to carry out a wide range of networking experiments

AN ADOPTIVE AND RESILIENT SEGMENT ROUTING VERSION 6 POLICY TO ADDRESS TIGHT SERVICE LEVEL AGREEMENT REQUIREMENTS IN 5G NETWORKS

There is ongoing work positioning Segment Routing version 6 (SRv6) as a replacement to General Packet Radio Service (GPRS) Tunneling Protocol User Plane (GTP-U). The main benefits of using SRv6 include coupling of the mobility overlay with the underlay (transport Traffic Engineering (TE)) and service chaining (GiLAN) and reusing high performance routers with SRv6 capabilities as User Plane Functions (UPFs). Techniques are described herein for enabling the creation of specific network slices where in the underlay a high resiliency is achieved with zero packet loss for tight Service Level Agreement (SLA) enterprise premium traffic. This same mechanism may be reused for path monitoring (e.g., latency, jitter, etc.) using in-band mechanisms for Ultra-Reliable Low Latency Communications (URLLC)

A NOVEL IP LOOKUP ALGORITHM WITH A MINIMAL PERFECT HASH FUNCTION FOR HIGH PERFORMANCE ROUTERS BASED ON NETFPGA

This thesis work shows the implementation of a new solution for the IP lookup function carried out by routers in a network. Packet forwarding in IP routers is performed according to the packet destination address which is matched, in a Longest Prefix Match(LPM) fashion, against several thousands of entries in a "Forwarding Table". This search for the Longest Prefix Match of the IP destination address is commonly referred to as IP lookup. The explosive growth of the Internet has translated into an unceasing reduction of the time-budget for packet processing and a growth of the number of entries in the Forwarding Tables, therefore this fundamental yet simple functionality has now become a critical task, which can often be the bottleneck in high performance routers. That is why a large variety of new algorithms have been presented, trying to improve the efficiency and speed of the lookup. The Algorithm here proposed is based on data structures called Blooming Trees, compact and fast techniques for membership queries. A Blooming Tree is a Bloom Filter based structure, which takes advantage of low false positive probability in order to reduce the mean number of memory accesses. The number of required memory accesses is one of the most important evaluation criterion for the quality of an algorithm for high performance routers, given that it strongly influences the mean time required for a lookup process. An array of parallel Blooming Trees accomplishes the Longest Prefix Match function for the entries of the Forwarding Table by storing the entries belonging to the 16--32 bit range. Shorter entries, intead, are stored in a very simple Direct Addressing logical block. Direct Addressing uses the address itself (in this case only the 15 most significant bits) as on offset to memory locations. Every Blooming Tree (hereafter BT) has been set up according to the MPH function, a scheme conceived to obtain memory efficient storage and fast item retrieval. The implementation platform for this algorithm is the NetFPGA board, a new networking hardware which proves to be a perfect tool for research and experimentation. It is composed of a full programmable Field Programmable Gate Array (FPGA) core, four Gigabit Ethernet ports and four banks of Static and Dynamic Random Access Memories (S/DRAM). NetFPGA has been designed as part of the Stanford University project named Clean Slate, a program which focuses on unconventional, bold, and long-term research that tries to break the network's ossification in order to improve it. This work is primarily focused on the central FPGA, where the Verilog language, an Hardware Description Language (HDL) describing directly the bit flows over the AND/OR/NOT ports, is adopted. In details, a set of static Blooming Trees structure is associated to the actual Forwarding Table and stored in fast Block on-chip RAM, while a second structure that stores the next-hop data is located onto the bigger NetFPGA SRAM. The lookup mechanism consists of a query in the BT array searching for a match and, in the case of a positive search, a query to the SRAM is performed in order to verify the matching. Since a BT always provides a non-zero false positive probability there could be an erroneous matching: in this case a new query is carried out. Finally if there is no correspondence for the searched IP address in the BT block of the algorithm, a simple Direct Addressing of the 15 most significant bits is done. A software control plane manages the algorithm, controlling the database construction and its update (adding or removing entries). In this sense the control module merges perfectly in the preexistent SCONE (Software Component of the NetFPGA)

Intelligent Packet Discard Policies for Improved TCP Queue Management

Recent studies have shown that suitably-designed packet discard policies can dramatically improve the performance of fair queueing mechanisms in internet routers. The Queue State Deficit Round Robin algorithm (QSDRR) preferentially discards from long queues, but in-troduces hysteresis into the discard policy to minimize synchronization among TCP flows. QSDRR provides higher throughput and much better fairness than simpler queueing mech-anisms, such as Tail-Drop, RED and Blue. However, because QSDRR discards packets that have previously been queued, it can signficantly increase the memory bandwidth require-ments of high performance routers. In this paper, we explore alternatives to QSDRR that provide comparable performance, while allowing packets to be discarded on arrival, saving memory bandwidth. Using ns-2 simulations, we show that the revised algorithms can come close to matching the performance of QSDRR and substantially outperform RED and Blue. Given a traffic mix of TCP flows with different round-trip times, longer round-trip time flows achieve 80% of their fair-share using the revised algorithms, compared to 40% under RED and Blue. We observe a similar improvement in fairness for long multi-hop paths competing against short cross-traffic paths. We also show that these algorithms can provide good performance, when each queue is shared among multiple flows

Modular router architecture for high-performance interconnection networks

Usmjerivači (ruteri) velikog kapaciteta su temeljni moduli mreža za široku međupovezanost sustava u računalnim sustavima velikog kapaciteta. Kolektivnom interakcijom oni osiguravaju pouzdanu komunikaciju između računalnih čvorova i upravljaju komunikacijskim protokom podataka. Postupak razvoja specijalizirane arhitekture usmjerivača vrlo je složen i zahtijeva razmatranje mnogih čimbenika. Arhitektura usmjerivača velikog kapaciteta uvelike ovisi o mehanizmu za reguliranje protoka budući da on upravlja načinom na koji se paketi prenose kroz mrežu. U radu se predlaže nova visoko učinkovita arhitektura usmjerivača "Step-Back-On-Blocking".High performance routers are fundamental building blocks of the system wide interconnection networks for high performance computing systems. Through collective interaction they provide reliable communication between the computing nodes and manage the communicational dataflow. The development process of specialized router architecture has high complexity and it requires many factors to be considered. The architecture of the high-performance routers is highly dependent on the flow control mechanism, as it dictates the way in which the packets are transferred through the network. In this paper novel high-performance "Step-Back-On-Blocking" router architecture has been proposed

An algorithm for fast route lookup and update

Increase in routing table sizes, number of updates, traffic, speed of links and migration to IPv6 have made IP address lookup, based on longest prefix matching, a major bottleneck for high performance routers. Several schemes are evaluated and compared based on complexity analysis and simulation results. A trie based scheme, called Linked List Cascade Addressable Trie (LLCAT) is presented. The strength of LLCAT comes from the fact that it is easy to be implemented in hardware, and also routing table update operations are performed incrementally requiring very few memory operations guaranteed for worst case to satisfy requirements of dynamic routing tables in high speed routers. Application of compression schemes to this algorithm is also considered to improve memory consumption and search time. The algorithm is implemented in C language and simulation results with real-life data is presented along with detailed description of the algorithm

Experimental Evaluation of a Coarse-Grained Switch Scheduler

Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Regulating the flow of packets through these interconnects is critical to providing good performance, particularly in the presence of extreme traffic patterns that result in sustained overload at output ports. Previous studies have used a combination of analysis and idealized simulations to show that coarse-grained scheduling of traffic flows can be effective in preventing congestion, while ensuring high utilization. In this paper, we study the performance of a coarse-grained scheduler in a real router with a scalable architecture similar to those found in high performance commercial systems. Our results are obtained by taking fine-grained measurements of an operating router that provide a detailed picture of how the scheduling algorithm behaves under a variety of conditions, giving a more complete and realistic understanding of the short time-scale dynamics than previous studies could provide. We also examine computation and communication overheads of our scheduler implementation to assess its resource usage and to provide the basis for an analysis of how the resource usage scales with system size

Effective video multicast over wireless internet

With the rapid growth of wireless networks and great success of Internet video, wireless video services are expected to be widely deployed in the near future. As different types of wireless networks are converging into all IP networks, i.e., the Internet, it is important to study video delivery over the wireless Internet. This paper proposes a novel end-system based adaptation protocol calledWireless Hybrid Adaptation Layered Multicast (WHALM) protocol for layered video multicast over wireless Internet. In WHALM the sender dynamically collects bandwidth distribution from the receivers and uses an optimal layer rate allocation mechanism to reduce the mismatches between the coarse-grained layer subscription levels and the heterogeneous and dynamic rate requirements from the receivers, thus maximizing the degree of satisfaction of all the receivers in a multicast session. Based on sampling theory and theory of probability, we reduce the required number of bandwidth feedbacks to a reasonable degree and use a scalable feedback mechanism to control the feedback process practically. WHALM is also tuned to perform well in wireless networks by integrating an end-to-end loss differentiation algorithm (LDA) to differentiate error losses from congestion losses at the receiver side. With a series of simulation experiments over NS platform, WHALM has been proved to be able to greatly improve the degree of satisfaction of all the receivers while avoiding congestion collapse on the wireless Internet