77 research outputs found
Doctor of Philosophy
dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency
A 2.4 GHz Phase Modulator for a WLAN OFDM Polar Transmitter in 0.18 um CMOS
This research focuses on the design and implementation of a digital active phase modulator path of a polar transmitter in the case of orthogonal frequency division multiplex WLAN application. The phase modulation path of the polar transmitter provides a constant envelope phase modulated signal to the Power amplifier(PA) , operating in nonlinear high efficient switching mode. The core design of the phase modulator is based on linear vector-sum phase shifting topology to differential quadrature input signals. The active phase shifter consists of a DAC that generates binary weighted currents for I and Q branches and differential signed adder that vector-sums the generated quadrature currents to generate the phase at the output.6 bits control the phase shifter, creating 64 states with the resolution of 5:625° for the whole 360°. The linear (binary weighted) vector-sum technique generates a reduction in the resultant amplitude that should be taken into consideration in case of nonlinear PA in polar transmission. On the other hand, the digital phase information is applied as the control bits to the phase shifter that determine the weightings and the signs of the I and Q vectors. The key point is the operation of the phase modulator in terms of phase accuracy, with the wideband modulation standard such as OFDM WLAN.
A technique has been proposed to enable the polar phase modulator to operate with a real-time wideband data and to compensate for the phase shifter output reduction. Since the reduction in gain is due to vector sum resultant of I and Q currents, it is compensated by modifying the I and Q currents for each 64 phase states. The design is implemented using 0.18 um CMOS technology and measured with maximum data rate of 64 QAM,OFDM modulation of WLAN standard. The output amplitude of the phase shifter with the correction technique is approximately constant over the 64 states with maximum variation of 3.5mv from the constant peak to peak value. The maximum achieved phase error is about 2° with a maximum DNL of 0.257
Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs
abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201
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Linearization techniques to suppress optical nonlinearity
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations
Digital polar transmitter for multi-band OFDM ultra-wideband
Master'sMASTER OF ENGINEERIN
Linearization techniques to suppress optical nonlinearity
This thesis is shown the implementation of the linearization techniques such as feedforward and pre-distortion feedback linearization to suppress the optical components nonlinearities caused by the fibre and semiconductor optical amplifier (SOA). The simulation verified these two linearization techniques for single tone direct modulation, two tone indirect modulation and ultra wideband input to the optical fibre. These techniques uses the amplified spontaneously emission (ASE) noise reduction in two loops of SOA by a feed-forward and predistortion linearizer and is shown more than 6dB improvement. Also it investigates linearization for the SOA amplifier to cancel out the third order harmonics or inter-modulation distortion (IMD) or four waves mixing. In this project, more than 20 dB reductions is seen in the spectral re-growth caused by the SOA. Amplifier non-linearity becomes more severe with two strong input channels leading to inter-channel distortion which can completely mask a third adjacent channel. The simulations detailed above were performed utilizing optimum settings for the variable gain, phase and delay components in the error correction loop of the feed forward and Predistortion systems and hence represent the ideal situation of a perfect feed-forward and Predistortion system. Therefore it should be consider that complexity of circuit will increase due to amplitude, phase and delay mismatches in practical design. Also it has describe the compatibility of Software Defined Radio with Hybrid Fibre Radio with simulation model of wired optical networks to be used for future research investigation, based on the star and ring topologies for different modulation schemes, and providing the performance for these configurations.EThOS - Electronic Theses Online ServiceGBUnited Kingdo
Linear Operation of Switch-Mode Outphasing Power Amplifiers
Radio transceivers are playing an increasingly important role in modern society. The
”connected” lifestyle has been enabled by modern wireless communications. The demand
that has been placed on current wireless and cellular infrastructure requires increased spectral
efficiency however this has come at the cost of power efficiency. This work investigates
methods of improving wireless transceiver efficiency by enabling more efficient power
amplifier architectures, specifically examining the role of switch-mode power amplifiers in
macro cell scenarios. Our research focuses on the mechanisms within outphasing power
amplifiers which prevent linear amplification. From the analysis it was clear that high power
non-linear effects are correctable with currently available techniques however non-linear effects
around the zero crossing point are not. As a result signal processing techniques for suppressing
and avoiding non-linear operation in low power regions are explored. A novel method of digital
pre-distortion is presented, and conventional techniques for linearisation are adapted for the
particular needs of the outphasing power amplifier. More unconventional signal processing
techniques are presented to aid linearisation of the outphasing power amplifier, both zero
crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear
regions of the amplifiers. In combination with digital pre-distortion the techniques
will improve linearisation efforts on outphasing systems with dynamic range and bandwidth
constraints respectively.
Our collaboration with NXP provided access to a digital outphasing power amplifier,
enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural
modelling and linearisation efforts. The collaboration resulted in a bench mark for linear
wideband operation of a digital outphasing power amplifier. The complimentary linearisation
techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in
both simulated and practical outphasing test benches. Initial results are promising and indicate
that the benefits they provide are not limited to the outphasing amplifier architecture alone.
Overall this thesis presents innovative analysis of the distortion mechanisms of the
outphasing power amplifier, highlighting the sensitivity of the system to environmental effects.
Practical and novel linearisation techniques are presented, with a focus on enabling wide band
operation for modern communications standards
Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas
This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next
generation 5G wireless network structure will be heterogeneous, the device
density and their mobility will increase and massive MIMO connectivity
capability will be widespread, the main investigated problem is formulated –
increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks.
The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes.
The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the
introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included.
The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation.
The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions.
The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and
measurement results for all designed radio frequency power amplifiers.
General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation.
5 papers, focusing on the subject of the discussed dissertation, have been
published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made
9 presentations at 9 scientific conferences at a national and international level.Dissertatio
A digital polar transmitter for multi-band OFDM Ultra-WideBand
Linear power amplifiers used to implement the Ultra-Wideband standard must be
backed off from optimum power efficiency to meet the standard specifications and
the power efficiency suffers. The problem of low efficiency can be mitigated by polar
modulation. Digital polar architectures have been employed on numerous wireless
standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved
are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm.
Can the architecture be employed on wireless standards with low-power and high
fractional bandwidth requirements and yet achieve good power efficiency?
To answer these question, this thesis studies the application of a digital polar transmitter
architecture with parallel amplifier stages for UWB. The concept of the digital
transmitter is motivated and inspired by three factors. First, unrelenting advances
in the CMOS technology in deep-submicron process and the prevalence of low-cost
Digital Signal processing have resulted in the realization of higher level of integration
using digitally intensive approaches. Furthermore, the architecture is an evolution
of polar modulation, which is known for high power efficiency in other wireless applications.
Finally, the architecture is operated as a digital-to-analog converter which
circumvents the use of converters in conventional transmitters.
Modeling and simulation of the system architecture is performed on the Agilent Advanced
Design System Ptolemy simulation platform. First, by studying the envelope
signal, we found that envelope clipping results in a reduction in the peak-to-average
power ratio which in turn improves the error vector magnitude performance (figure
of merit for the study). In addition, we have demonstrated that a resolution of three
bits suffices for the digital polar transmitter when envelope clipping is performed.
Next, this thesis covers a theoretical derivation for the estimate of the error vector
magnitude based on the resolution, quantization and phase noise errors. An analysis
on the process variations - which result in gain and delay mismatches - for a
digital transmitter architecture with four bits ensues. The above studies allow RF
designers to estimate the number of bits required and the amount of distortion that
can be tolerated in the system.
Next, a study on the circuit implementation was conducted. A DPA that comprises
7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7
cascode transistors (individually connected in series with the bottom amplifiers)
digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB
signal at the output. Through the use of NFET models from the IBM 130-nm
technology, our simulation reveals that our DPA is able to achieve an EVM of -
22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency
with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth
of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering
-1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power.
In addition, we performed a yield analysis on the digital polar amplifier, based
on unit-weighted and binary-weighted architecture, when gain variations are introduced
in all the individual stages. The dynamic element matching method is also
introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations
reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a
standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%,
while the yields of the unit-weighted architectures are in the neighbourhood of 95%.
Moreover, the dynamic element matching technique demonstrates an improvement
in the yield by approximately 3%.
Finally, a hardware implementation for this architecture based on software-defined
arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar
transmitter under ideal combining conditions fulfill the European Computer Manufacturers
Association requirements. The proposed experimental setup, believed to
be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture
for Ultra-Wideband. In addition, we propose a number of power combining
techniques suitable for the hardware implementation. Spatial power combining, in
particular, shows a high potential for the digital polar transmitter architecture.
The above studies demonstrate the feasibility of the digital polar architecture with
good power efficiency for a wideband wireless standard with low-power and high
fractional bandwidth requirements
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