Electrochemically deposited germanium on silicon and its crystallization by rapid melting growth

It is well known that continuous miniaturization of transistors tends to create several problems such as current leakage, short channel effect, etc. Therefore, introduction of new channel material with higher carrier mobilities such as Germanium (Ge) is suggested to overcome this physical limitation and also to improve the performance of conventional transistors in chips. Basically, there are several techniques to grow Ge such as Chemical Vapour Deposition (CVD) and Molecular Beam Epitaxy (MBE) system. However, these processes require high vacuum environment, highly depend on such hard-to-control variables as well as costly. Therefore, an alternative method that practically cheaper to grow Ge utilizing electrochemical and rapid melting technique is investigated here. In this thesis, a systematic study of electrochemical deposition of Ge on Silicon (Si) substrate is outlined. Results show the unwanted Germanium Dioxide (GeO2) tends to form in the air-exposed process and germanium tetrachloride:dipropylene glycol (GeCl4:C6H14O3) electrolyte. Therefore, a Nitrogen (N2) controlled ambient is preferable. The uniform amorphous Ge film on Si (100) substrate was successfully obtained at the optimum current density of 20 mAcm-2 in germanium tetrachloride:propylene glycol (GeCl4:C3H8O2) electrolyte. Crystallization of electrodeposited Ge on Si (100) was demonstrated by rapid melting process. Effect of different annealing temperatures from 1000 to 1100 oC has also been studied. Raman spectra and Electron Backscattering Diffraction (EBSD) result confirmed that the grown Ge was highly oriented with the crystal orientation identical to that of Si (100) substrate at all annealing temperature tested. Based on depth profile from Auger Electron Spectroscopy (AES) measurement and Raman spectra, it was found that Si-Ge mixing occurred upon rapid melting process, particularly at near the Si-Ge interface caused by atoms diffusion. Calculated Si fraction diffused into Ge region in the Si-Ge mixing was high at higher annealing temperature that shows good agreement with solidus curve of Ge-Si equilibrium phase diagram. Correspondingly, the amount of Ge diffused into Si region also increased as annealing temperature increased. The result also shows that the tensile strain turns from high to low with the increase of annealing temperature. In addition, it drastically becomes more compressive as the depth is approaching the interface of Ge and Si. The difference in thermal expansion coefficient is a possible cause to generate such strain behaviour. For applications, the presence of strain in channel will improve the transistor performance by enhancing the carrier mobility. In conclusion, this study proves that electrochemical deposition and rapid melting growth technique are promising methods for synthesizing crystalline Ge and significantly contribute to the improvement of carrier mobility. It is expected that high performance Complementary Metal Oxide Semiconductor (CMOS) transistor scaling and Moore’s Law will continue in the future through new materials introduction in the transistor structure and by incorporating significantly appropriate levels of strain and composition of Ge/Si in the channel

Study of a New Silicon Epitaxy Technique: Confined Lateral Selective Epitaxial Growth

This work describes a significant new advance in the technique of silicon selective epitaxy called Confined Lateral Selective Epitaxial Growth (CLSEG). CLSEG is a method for forming thin films of single crystal silicon on top of an insulating layer or film. Such thin films are generically termed Silicon-On- Insulator (SOI), and1 allow dielectric isolation of integrated circuit elements, making them more efficient (faster with lower power), more resistant to radiation, and smaller than conventional integrated circuits, ionizing radiation than conventional integrated circuits. CLSEG offers advantages over current methods of achieving SOI by being easily manufactured, inherently reproducible, and having greater design flexibility. CLSEG is also adaptable to vertical stacking of devices in a circuit, in what is called three-dimensional integration, for even greater reductions in area. In addition, CLSEG can be used for a wide variety of sensor and micromachining application. This thesis describes the design and development of CLSEG, and compares it to the current state of the art in the fields of SOI and Selective Epitaxial Growth (SEG). CLSEG is accomplished by growing silicon selective epitaxy within a cavity; which is formed of dielectric materials upon a silicon substrate. The resulting SOI film can be made as thin as 0.1 micron, and tens of microns wide, with an unlimited length. In particular, there is now strong evidence that surface diffusivity of silicon adatoms on the dielectric masking layers is a significant contributor to the transport of silicon to the growth surface during SE G. CLSEG silicon material quality is evaluated by fabricating a variety of semiconductor devices in CLSEG films. These devices demonstrate the applicability of CLSEG to integrated circuits, and provide a basis of comparison between CLSEG-grown silicon and device-quality substrate silicon. Then, CLSEG is used to fabricate an advanced device structure, verifying the value and significance of this new epitaxy technique. In the final two chapters, CLSEG is evaluated as a technology, and compared to the current state of the art. Then, a method is presented Tor forming CLSEG with only one photolithography step, and a process is described for making a SOI film across an entire silicon wafer using CLSEG. These techniques may indicate the feasibility of using CLSEG for three dimensional integration of microelectronics. It is hoped that this work will establish a firm basis for further study of this interesting and valuable new technology

Proceedings of the Second Caltech Conference on Very Large Scale Integration, held at the California Institute of Technology 19-21 January, 1981 ; Organized by the Caltech Computer Science Department and the Caltech Industrial Associates Office, and sponsored by Caltech Industrial Associates and the National Science Foundation

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Onboard Experiment Data Support Facility

An onboard array structure has been devised for end to end processing of data from multiple spaceborne sensors. The array constitutes sets of programmable pipeline processors whose elements perform each assigned function in 0.25 microseconds. This space shuttle computer system can handle data rates from a few bits to over 100 megabits per second

Technology 2003: The Fourth National Technology Transfer Conference and Exposition, volume 2

Proceedings from symposia of the Technology 2003 Conference and Exposition, Dec. 7-9, 1993, Anaheim, CA, are presented. Volume 2 features papers on artificial intelligence, CAD&E, computer hardware, computer software, information management, photonics, robotics, test and measurement, video and imaging, and virtual reality/simulation

Reports to the President

A compilation of annual reports for the 1999-2000 academic year, including a report from the President of the Massachusetts Institute of Technology, as well as reports from the academic and administrative units of the Institute. The reports outline the year's goals, accomplishments, honors and awards, and future plans

Research and technology operating plan: A summary Fiscal Year 1974

A compilation is presented of the summary portions of RTOPs used for management review and control of research. Citations and abstracts of RTOPs are included. A list is presented of RTOPs which have been changed, completed, or terminated since the last summary. Indexes presented include: subject, technical monitor, responsible NASA organization, and RTOP number