Design of Power Receiving Units for 6.78MHz Wireless Power Transfer Systems

In the last decade, the wireless power transfer (WPT) technology has been a popular topic in power electronics research and increasingly adopted by consumers. The AirFuel WPT standard utilizes resonant coils to transfer energy at 6.78 MHz, introducing many benefits such as longer charging distance, multi-device charging, and high tolerance of the coil misalignment. However, variations in coil coupling due to the change in receiving coil positions alter the equivalent load reactance, degrading efficiency. In recent studies, active full-bridge rectifiers are employed on WPT receivers because of their superior efficiency, controllability, and ability to compensate for detuned WPT networks. In order to take advantage of those characteristics, the rectifier switching actions must be synchronized with the magnetic field. In the literature, existing solutions for synchronizing the active rectifier in WPT systems are mostly not reliable and bulky, which is not suitable for small receivers. Therefore, a frequency synchronous rectifier with compact on-board control is proposed in this thesis. The rectifier power stage is designed to deliver 40 W to the load while achieving full zero-voltage switching to minimize the loss. The inherent feedback from the power stage dynamics to the sensed signal is analyzed to design stable and robust synchronization control, even at a low power of 0.02 W. The control system is accomplished using commercial components, including a low-cost microcontroller, which eliminates the need for bulky control and external sensing hardware. This high power density design allows the receiver to be integrated into daily consumer electronics such as laptops and monitors. Finally, a wide-range and high v resolution control scheme of the rectifier input phase is proposed to enable the dynamic impedance matching capability, maintaining high system efficiency over wide loading conditions. In addition, to increase the WPT technology adoption to low-power consumer electronics, a small wireless receiver replacing conventional AA batteries is developed. This receiver can supply power to existing AA battery-powered devices while providing the benefit of WPT technologies to consumers

Design of frequency synthesizers for short range wireless transceivers

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts

Nonintrusive Flowmeter

The results of analytical and experimental work performed in the design, fabrication, and test of a prototype nonintrusive gaging system for use in monitoring the consumption of earth-storable fuels and oxidants in either a one-g or a zero-g environment are explained. The design specifications were those applicable to the reaction control system and to the orbital maneuvering system (OMS) fuel and oxidant on the space shuttle while in orbit. The major requirement was for the measurement of flow pulses with sufficient accuracy to provide a continuous knowledge of the fuel and oxidant remaining in the OMS system to within 1% or better. An ultrasonic frequency chirp technique was used having a high inherent rejection for signals traversing stray paths, and for random noise generated by the flowing liquid. A detailed analysis of the frequency chirp approach for two modes of operation (period and phase changes), including an error analysis are reported

A high speed serializer/deserializer design

A Serializer/Deserializer (SerDes) is a circuit that converts parallel data into a serial stream and vice versa. It helps solve clock/data skew problems, simplifies data transmission, lowers the power consumption and reduces the chip cost. The goal of this project was to solve the challenges in high speed SerDes design, which included the low jitter design, wide bandwidth design and low power design. A quarter-rate multiplexer/demultiplexer (MUX/DEMUX) was implemented. This quarter-rate structure decreases the required clock frequency from one half to one quarter of the data rate. It is shown that this significantly relaxes the design of the VCO at high speed and achieves lower power consumption. A novel multi-phase LC-ring oscillator was developed to supply a low noise clock to the SerDes. This proposed VCO combined an LC-tank with a ring structure to achieve both wide tuning range (11%) and low phase noise (-110dBc/Hz at 1MHz offset). With this structure, a data rate of 36 Gb/s was realized with a measured peak-to-peak jitter of 10ps using 0.18microm SiGe BiCMOS technology. The power consumption is 3.6W with 3.4V power supply voltage. At a 60 Gb/s data rate the simulated peak-to-peak jitter was 4.8ps using 65nm CMOS technology. The power consumption is 92mW with 2V power supply voltage. A time-to-digital (TDC) calibration circuit was designed to compensate for the phase mismatches among the multiple phases of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D process. Mismatches caused by the vertical tier-to-tier interconnections and the temperature influence in the 3D process were attenuated by the proposed calibration circuit. The design strategy and circuits developed from this dissertation provide significant benefit to both wired and wireless applications

Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.

Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15