1,857 research outputs found
High Density Through Silicon Via (TSV)
The Through Silicon Via (TSV) process developed by Silex provides down to 30
micrometers pitch for through wafer connections in up to 600 micrometers thick
substrates. Integrated with MEMS designs it enables significantly reduced die
size and true "Wafer Level Packaging" - features that are particularly
important in consumer market applications. The TSV technology also enables
integration of advanced interconnect functions in optical MEMS, sensors and
microfluidic devices. In addition the Via technology opens for very interesting
possibilities considering integration with CMOS processing. With several
companies using the process already today, qualified volume manufacturing in
place and a line-up of potential users, the process is becoming a standard in
the MEMS industry. We provide a introduction to the via formation process and
also present some on the novel solutions made available by the technology.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/handle/2042/16838
Electrical and mechanical analysis of different TSV geometries
Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. By facilitating the stacking of silicon chips, the TSV technology also helps to meet the increasing demand for high density and high performance miniaturized electronic products. Our review of the literature shows that very few studies have reported on the impact of TSV bump geometry on the electrical and mechanical characteristics of the TSV. This paper reports on the investigation of different TSV geometries with the focus on identifying the ideal shapes for improved electrical signal transmission as well as for improved mechanical reliability. The cylindrical, quadrangular (square), elliptical, and triangular shapes were investigated in our study and our results showed that the quadrangular shape had the best electrical performance due to good characteristic impedance. Our results also showed that the quadrangular and cylindrical shapes provided improved mechanical reliability as these two shapes lead to high Cu protrusion of TSV after the annealing process
Technologies for 3D Heterogeneous Integration
3D-Integration is a promising technology towards higher interconnect
densities and shorter wiring lengths between multiple chip stacks, thus
achieving a very high performance level combined with low power consumption.
This technology also offers the possibility to build up systems with high
complexity just by combining devices of different technologies. For ultra thin
silicon is the base of this integration technology, the fundamental processing
steps will be described, as well as appropriate handling concepts. Three main
concepts for 3D integration have been developed at IZM. The approach with the
greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion
(ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which
combines the advantages of the Inter Chip Via (ICV) process and the
solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully
modular ICV-SLID concept allows the formation of multiple device stacks. A test
chip was designed and the total process sequence of the ICV-SLID technology for
the realization of a three-layer chip-to-wafer stack was demonstrated. The
proposed wafer-level 3D integration concept has the potential for low cost
fabrication of multi-layer high-performance 3D-SoCs and is well suited as a
replacement for embedded technologies based on monolithic integration. To
address yield issues a wafer-level chip-scale handling is presented as well, to
select known-good dies and work on them with wafer-level process sequences
before joining them to integrated stacks.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/handle/2042/16838
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Characterization Of Thermal Stresses And Plasticity In Through-Silicon Via Structures For Three-Dimensional Integration
Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in the TSV structure to cause reliability problems. In this study, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure. The thermo-mechanical characteristics of the Cu TSV structure were correlated to microstructure evolution during thermal cycling and the local plasticity in Cu in a triaxial stress state. These findings were confirmed by microstructure analysis of the Cu vias and finite element analysis (FEA) of the stress characteristics. In addition, the local plasticity and deformation in and around individual TSVs were measured by synchrotron x-ray microdiffraction to supplement the wafer curvature measurements. The importance and implication of the local plasticity and residual stress on TSV reliabilities are discussed for TSV extrusion and device keep-out zone (KOZ).Microelectronics Research Cente
Design of TSV-sharing topologies for cost-effective 3D networks-on-chip
The Through-Silicon Via (TSV) technology has led to major breakthroughs in 3D stacking by providing higher speed and bandwidth, as well as lower power dissipation for the inter-layer communication. However, the current TSV fabrication suffers from a considerable area footprint and yield loss. Thus, it is necessary to restrict the number of TSVs in order to design cost-effective 3D on-chip networks. This critical issue can be addressed by clustering the network such that all of the routers within each cluster share a single TSV pillar for the vertical packet transmission. In some of the existing topologies, additional cluster routers are augmented into the mesh structure to handle the shared TSVs. However, they impose either performance degradation or power/area overhead to the system. Furthermore, the resulting architecture is no longer a mesh. In this paper, we redefine the clusters by replacing some routers in the mesh with the cluster routers, such that the mesh structure is preserved. The simulation results demonstrate a better equilibrium between performance and cost, using the proposed models
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity
Various side-channel attacks (SCAs) on ICs have been successfully
demonstrated and also mitigated to some degree. In the context of 3D ICs,
however, prior art has mainly focused on efficient implementations of classical
SCA countermeasures. That is, SCAs tailored for up-and-coming 3D ICs have been
overlooked so far. In this paper, we conduct such a novel study and focus on
one of the most accessible and critical side channels: thermal leakage of
activity and power patterns. We address the thermal leakage in 3D ICs early on
during floorplanning, along with tailored extensions for power and thermal
management. Our key idea is to carefully exploit the specifics of material and
structural properties in 3D ICs, thereby decorrelating the thermal behaviour
from underlying power and activity patterns. Most importantly, we discuss
powerful SCAs and demonstrate how our open-source tool helps to mitigate them.Comment: Published in Proc. Design Automation Conference, 201
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