2,235 research outputs found
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
Mapping constrained optimization problems to quantum annealing with application to fault diagnosis
Current quantum annealing (QA) hardware suffers from practical limitations
such as finite temperature, sparse connectivity, small qubit numbers, and
control error. We propose new algorithms for mapping boolean constraint
satisfaction problems (CSPs) onto QA hardware mitigating these limitations. In
particular we develop a new embedding algorithm for mapping a CSP onto a
hardware Ising model with a fixed sparse set of interactions, and propose two
new decomposition algorithms for solving problems too large to map directly
into hardware.
The mapping technique is locally-structured, as hardware compatible Ising
models are generated for each problem constraint, and variables appearing in
different constraints are chained together using ferromagnetic couplings. In
contrast, global embedding techniques generate a hardware independent Ising
model for all the constraints, and then use a minor-embedding algorithm to
generate a hardware compatible Ising model. We give an example of a class of
CSPs for which the scaling performance of D-Wave's QA hardware using the local
mapping technique is significantly better than global embedding.
We validate the approach by applying D-Wave's hardware to circuit-based
fault-diagnosis. For circuits that embed directly, we find that the hardware is
typically able to find all solutions from a min-fault diagnosis set of size N
using 1000N samples, using an annealing rate that is 25 times faster than a
leading SAT-based sampling method. Further, we apply decomposition algorithms
to find min-cardinality faults for circuits that are up to 5 times larger than
can be solved directly on current hardware.Comment: 22 pages, 4 figure
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Silicon compilation
Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory
Edge Routing with Ordered Bundles
Edge bundling reduces the visual clutter in a drawing of a graph by uniting
the edges into bundles. We propose a method of edge bundling drawing each edge
of a bundle separately as in metro-maps and call our method ordered bundles. To
produce aesthetically looking edge routes it minimizes a cost function on the
edges. The cost function depends on the ink, required to draw the edges, the
edge lengths, widths and separations. The cost also penalizes for too many
edges passing through narrow channels by using the constrained Delaunay
triangulation. The method avoids unnecessary edge-node and edge-edge crossings.
To draw edges with the minimal number of crossings and separately within the
same bundle we develop an efficient algorithm solving a variant of the
metro-line crossing minimization problem. In general, the method creates clear
and smooth edge routes giving an overview of the global graph structure, while
still drawing each edge separately and thus enabling local analysis
An automated routing method for VLSI with three interconnection layers
Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. In this thesis, we examine the VLSI routing problem where three layers are available for interconnection;We investigate the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for three-interconnection layer model is not much different from that of two-layer madel. We study the global routing problem for two cases: gate array and general cell layout. In our three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on;The channel routing stage of our router is based on directional model where overlaps of horizontal wire segments are allowed. We improve the dogleg method so that it is applicable to the three-layer model and it can handle multi-terminal nets more efficiently. Applying the extensive dogleg method and the three-layer merge algorithm, we not only remove the cyclic vertical constraints graph but also eliminate the effect of the height of long vertical constraints tree to the channel width and thus we reduce the lower bound of the channel width to half of the density of the channel. We expand the applicability of channel router by eliminating some of the limitations assumed in channel routing problems by some existing algorithms. Routability conditions are examined for various cases of channel routing problem;The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing which minimizes the channel width and the wire length. Experimental results show that our router is close to optimal
Design Methodology of Very Large Scale Integration
Very Large Scale Integration (VLSI) deals with systems complexity rather than transistor size or circuit performance. VLSI design methodology is supported by Computer Aided Design (CAD) and Design Automation (DA) tools, which help VLSI designers to implement more complex and guaranteed designs. The increasing growth in VLSI complexity dictates a hierarchical design approach and the need for hardware DA tools.
This paper discusses the generalized Design Procedure for CAD circuit design; the commercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools. A complete design of a Content Addressable Memory (CAM) cell, using the Caesar system, supported by Berkeley CAD tools, is illustrated
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