DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Numerical Simulations

This book will interest researchers, scientists, engineers and graduate students in many disciplines, who make use of mathematical modeling and computer simulation. Although it represents only a small sample of the research activity on numerical simulations, the book will certainly serve as a valuable tool for researchers interested in getting involved in this multidisciplinary field. It will be useful to encourage further experimental and theoretical researches in the above mentioned areas of numerical simulation

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts