17 research outputs found

    Hardware emulation of wireless communication fading channels

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    This dissertation investigates several main challenges to implementing hardware-based wireless fading channel emulators with emphasis on incorporating accurate correlation properties. Multiple-input multiple-output (MIMO) fading channels are usually triply-selective with three types of correlation: temporal correlation, inter-tap correlation, and spatial correlation. The proposed emulators implement the triply-selective fading Channel Impulse Response (CIR) by incorporating the three types of correlation into multiple uncorrelated frequency-flat Rayleigh fading waveforms while meeting real-time requirements for high data-rate, large-sized MIMO, and/or long CIR channels. Specifically, mixed parallel-serial computational structures are implemented for Kronecker products of the correlation matrices, which makes the best tradeoff between computational speed and hardware usage. Five practical fading channel examples are implemented for RF or underwater acoustic MIMO applications. The performance of the hardware emulators are verified with an Altera Field-Programmable Gate Array (FPGA) platform and the results match the software simulators in terms of statistical and correlation properties. The dissertation also contributes to the development of a 2-by-2 MIMO transceiver testbench that is used to measure real-world fading channels. Intensive channel measurements are performed for indoor fixed mobile-to-mobile channels and the estimated CIRs demonstrate the triply-selective correlation properties --Abstract, page iv

    Hardware Emulation of Wideband Correlated Multiple-input Multiple-output Fading Channels

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    A low-complexity hardware emulator is proposed for wideband, correlated, multiple-input multiple-output (MIMO) fading channels. the proposed emulator generates multiple discrete-time channel impulse responses (CIR) at the symbol rate and incorporates three types of correlation functions of the subchannels via Kronecker product: The spatial correlation between transmit or receive elements, temporal correlation due to Doppler shifts, and inter-tap correlation due to multipaths. the Kronecker product is implemented by a novel mixed parallel-serial (mixed P-S) matrix multiplication method to reduce memory storage and to meet the real-time requirement in high data-rate, large MIMO size, or long CIR systems. We present two practical MIMO channel examples implemented on an Altera Stratix III EP3SL150F FPGA DSP development kit: A 2-by-2 MIMO WiMAX channel with a symbol rate of 1.25 million symbols/second and a 2-by-6 MIMO underwater acoustic channel with 100-tap CIR. Both examples meet real-time requirement using only 12?14% of hardware resources of the FPGA. © Springer Science Business Media, LLC 2011

    A Fading Channel Simulator Implementation Based on GPU Computing Techniques

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    Channel simulators are powerful tools that permit performance tests of the individual parts of a wireless communication system. This is relevant when new communication algorithms are tested, because it allows us to determine if they fulfill the communications standard requirements. One of these tests consists of evaluating the system performance when a communication channel is considered. In this sense, it is possible to model the channel as an FIR filter with time-varying random coefficients. If the number of coefficients is increased, then a better approach to real scenarios can be achieved; however, in that case, the computational complexity is increased. In order to address this issue, a design methodology for computing the time-varying coefficients of the fading channel simulators using consumer-designed graphic processing units (GPUs) is proposed. With the use of GPUs and the proposed methodology, it is possible for nonspecialized users in parallel computing to accelerate their simulation developments when compared to conventional software. Implementation results show that the proposed approach allows the easy generation of communication channels while reducing the processing time. Finally, GPU-based implementation takes precedence when compared with the CPU-based implementation, due to the scattered nature of the channel. � 2015 R. Carrasco-Alvarez et al

    Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators

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    This thesis presents a new adaptive function segmentation methodology (AFSM), for the evaluation of mathematical functions through piecewise polynomial approximation (PPA) methods. This methodology is planned to be employed for the development of an efficient hardware-based channel emulator in future development steps of the current project. In contrast to state-of-art segmentation methodologies, which applicability is limited because these are highly dependent on the function shape and require significant intervention from the user to setup appropriately the algorithm, the proposed segmentation methodology is flexible and applicable to any continuous function within an evaluation interval. Through the analysis of the first and second order derivatives, the methodology becomes aware of the function shape and adapts the algorithm behavior accordingly. The proposed segmentation methodology aims towards hardware architectures of limited resources that resort to fixed-point numeric representation where hardware designer should make a compromise between resources consumption and output accuracy. An optimization algorithm is implemented to assist the user in searching the best segmentation parameters that maximize the outcome of the design trade-offs for a given signal-to-quantization-noise ratio requirement. When compared to state-of-the-art segmentation methodologies, the proposed AFSM delivers better performance of approximation for the hardware-based evaluation of transcendental functions given that fewer segments and consequently fewer hardware resources are required.Consejo Nacional de Ciencia y Tecnologí

    Advanced Applications of Rapid Prototyping Technology in Modern Engineering

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    Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

    Hardware implementation of triply selective Rayleigh fading channel simulators

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    Aeronautical Engineering: A continuing bibliography with indexes (supplement 188)

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    This bibliography lists 477 reports, articles and other documents introduced into the NASA scientific and technical information system in May 1985. The coverage includes documents on the engineering and theoretical aspects of design, construction, evaluation, testing, operation, and performance of aircraft (including aircraft engines) and associated components, equipment and systems

    Cumulative index to NASA Tech Briefs, 1986-1990, volumes 10-14

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    Tech Briefs are short announcements of new technology derived from the R&D activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This cumulative index of Tech Briefs contains abstracts and four indexes (subject, personal author, originating center, and Tech Brief number) and covers the period 1986 to 1990. The abstract section is organized by the following subject categories: electronic components and circuits, electronic systems, physical sciences, materials, computer programs, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences
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