QR codes decoder

The aim of this project is to develop a device that demonstrates the ability to read barcodes, and is also capable of detecting and analysing QR codes from a picture

VEHICLE RECOGNITION SYSTEM

The goal of this dissertation is to explain in detail the whole progress and overall process of the Vehicle Recognition System project in detail in term of completing the Final Year Project II. This report includes the background of study that describe about what the system is about, the problem statement with the current method, the objectives of developing the new system and the scope of study for the first chapter. In the Literature Review section, this report will explain the topic that is related about the system such as barcode methodology and symbologies. It also explains the programming language use as the database and the tools needed for implementing the project. In methodology section, it's described the method use for creating the system, the flow of that system and the tool used. The results and discussions section discuss in detail the requirement of the system before the system can implemented and lastly, the conclusion section will elaborate where the author concludes about the system that is to be developed briefly. It is important to develop this system as it will help the security to handle the UTP' s environment well

Method and Apparatus for Simultaneous Processing of Multiple Functions

Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described

Design and implementation of NoC routers and their application to Prdt-based NoC\u27s

With a communication-centric design style, Networks-on-Chips (NoCs) emerges as a new paradigm of Systems-on-Chips (SoCs) to overcome the limitations of bus-based communication infrastructure. An important problem in the design of NoCs is the router design, which has great impact on the cost and performance of a NoC system. This thesis is focused on the design and implementation of an optimized parameterized router which can be applied in mesh/torus-based and Perfect Recursive Diagonal Torus (PRDT)-based NoCs; In specific, the router design includes the design and implementation of two routing algorithms (vector routing and circular coded vector routing), the wormhole switching scheme, the scheduling scheme, buffering strategy, and flow control scheme. Correspondingly, the following components are designed and implemented: input controller, output controller, crossbar switch, and scheduler. Verilog HDL codes are generated and synthesized on ASIC platforms. Most components are designed in parameterized way. Performance evaluation of each component of the router in terms of timing, area, and power consumption is conducted. The efficiency of the two routing algorithms and tradeoff between computational time (tsetup) and area are analyzed; To reduce the area cost of the router design, the two major components, the crossbar switch and the scheduler, are optimized. Particularly, for crossbar switch, a comparative study of two crossbar designs is performed with the aid of Magic Layout editor, Synopsys CosmosSE and Awaves; Based on the router design, the PRDT network composed of 4x4 routers is designed and synthesized on ASIC platforms

Attention, Learn to Solve Routing Problems!

The recently presented idea to learn heuristics for combinatorial optimization problems is promising as it can save costly development. However, to push this idea towards practical implementation, we need better models and better ways of training. We contribute in both directions: we propose a model based on attention layers with benefits over the Pointer Network and we show how to train this model using REINFORCE with a simple baseline based on a deterministic greedy rollout, which we find is more efficient than using a value function. We significantly improve over recent learned heuristics for the Travelling Salesman Problem (TSP), getting close to optimal results for problems up to 100 nodes. With the same hyperparameters, we learn strong heuristics for two variants of the Vehicle Routing Problem (VRP), the Orienteering Problem (OP) and (a stochastic variant of) the Prize Collecting TSP (PCTSP), outperforming a wide range of baselines and getting results close to highly optimized and specialized algorithms.Comment: Accepted at ICLR 2019. 25 pages, 7 figure

Reticle management analysis for the photolithography sector of a semiconductor fabrication facility

Reticle management analysis for the photolithography sector of a semiconductor fabrication facilit

Method and Apparatus for Simultaneous Processing of Multiple Functions

Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described