Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs

International audienceOver the past 10 years, the designers of intellectual properties(IP) have faced increasing threats including cloning, counterfeiting, andreverse-engineering. This is now a critical issue for the microelectronicsindustry. The design of a secure, efficient, lightweight protection scheme fordesign data is a serious challenge for the hardware security community. In thiscontext, this chapter presents two ultra-lightweight transmitters using sidechannel leakage based on electromagnetic emanation to send embedded IPidentity discreetly and quickl

Clock-modulation based watermark for protection of embedded processors

This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98\% was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attack

Hardware Trojan Detection Using Machine Learning

The cyber-physical system’s security depends on the software and underlying hardware. In today’s times, securing hardware is difficult because of the globalization of the Integrated circuit’s manufacturing process. The main attack is to insert a “backdoor” that maliciously alters the original circuit’s behaviour. Such a malicious insertion is called a hardware trojan. In this thesis, the Random Forest Model has proposed for hardware trojan detection and this research focuses on improving the detection accuracy of the Random Forest model. The detection technique used the random forest machine learning model, which was trained by using the power traces of the circuit behaviour. The data required for training was obtained from an extensive database by simulating the circuit behaviours with various input vectors. The machine learning model was then compared with the state-of-art models in terms of accuracy in detecting malicious hardware. Our results show that the Random Forest classifier achieves an accuracy of 99.80 percent with a false positive rate (FPR)of 0.009 and a false negative rate (FNR) of 0.038 when the model is created to detect hardware trojans. Furthermore, our research shows that a trained model takes less training time and can be applied to large and complex datasets

Hardware Trojan Detection in Third Party Digital IP Cores

Due to Globalization outsourcing of SoC designs either for verification, testing and fabrication has become inevitable. Modern System on chip (SoC) is complex process. Modern SoC‟s can be designed time effectively and cost effectively with the help of third party Intellectual Property (IP) core vendors. Various processors cores (like ARM, Power PC), communication controllers (CAN, Zigbee) and control cores (PWM, Analog comparator) will get incorporated into SoC‟s, which are supplied by different vendors. The original SoC manufacturers are IP integrators, targeting a particular application. In this process, various issues like IP protection, IP rights and problem of malicious IP‟s will arise. Recent addition in this list is Hardware Trojans (HT). HT‟s can be included by rogue designer in design house or at overseas fabrication factories. The objective of these HT‟s includes manipulating the functionality of the chip, leaking confidential information and destroying the system. HT‟s included in the design phase must be weeded out during verification phase. Still now, there is no concrete method or golden rule in the existing verification framework to detect the HT‟s. Various verification metrics like code coverage, functional coverage and verification methodologies like OVM or UVM will be helpful in detecting HT‟s. Formal verification is also useful. A comprehensive framework using all verification metrics is very much required to detect HT‟s. We will address this issue in our thesis. Secondly, static timing analysis (STA) and power analysis (PA) can be used to detect HT‟s included at both design phase and also in fabrication. In our proposed framework, we will incorporate verification metrics, formal verification, STA and PA to detect HT‟s. In this report, we apply DFT techniques and standard verification metrics to detect the hardware Trojans. The microprocessors and cryptographic designs are most vulnerable for hardware Trojan attacks. The Advanced Encryption Standard (AES) and RSA Trojan benchmarks from Trust Hub are used to verify the existing test principles like stuck at fault (SAF), path delay faults (PDF) are capable of detecting Trojans in Benchmarks. Results and analysis is presented in this report. Also Novel Trojan Benchmarks designs were proposed to eliminate the existing weaknesses in AES Benchmarks

Break on Through: An Analysis of Computer Damage Cases

The following Article is an extensive inquiry into computer damage cases through a comprehensive study of over three hundred computer damage cases. Throughout the study, the authors have performed an empirical categorization of the essential aspects of computer damage cases and analyzed the most relevant issues, interpretations, and arguments available for each computer damage category. These categories include fundamental facets, such as legal elements; motive and intent; results; profile of perpetrators; and means of perpetration, including, if applicable, the software involved. The Article provides a comprehensive analysis and conceptual approach for understanding computer damage cases by discussing the legal elements of computer damage offenses under the CFAA; considering the CFAA’s practical application; discussing the essential features involved in the perpetration of computer damage offenses and profiling the attackers; and summarizing the researchers’ findings

Emerging Security Threats in Modern Digital Computing Systems: A Power Management Perspective

Design of computing systems — from pocket-sized smart phones to massive cloud based data-centers — have one common daunting challenge : minimizing the power consumption. In this effort, power management sector is undergoing a rapid and profound transformation to promote clean and energy proportional computing. At the hardware end of system design, there is proliferation of specialized, feature rich and complex power management hardware components. Similarly, in the software design layer complex power management suites are growing rapidly. Concurrent to this development, there has been an upsurge in the integration of third-party components to counter the pressures of shorter time-to-market. These trends collectively raise serious concerns about trust and security of power management solutions. In recent times, problems such as overheating, performance degradation and poor battery life, have dogged the mobile devices market, including the infamous recall of Samsung Note 7. Power outage in the data-center of a major airline left innumerable passengers stranded, with thousands of canceled flights costing over 100 million dollars. This research examines whether such events of unintentional reliability failure, can be replicated using targeted attacks by exploiting the security loopholes in the complex power management infrastructure of a computing system. At its core, this research answers an imminent research question: How can system designers ensure secure and reliable operation of third-party power management units? Specifically, this work investigates possible attack vectors, and novel non-invasive detection and defense mechanisms to safeguard system against malicious power attacks. By a joint exploration of the threat model and techniques to seamlessly detect and protect against power attacks, this project can have a lasting impact, by enabling the design of secure and cost-effective next generation hardware platforms