9 research outputs found
Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments
Field-Programmable Gate Arrays (FPGAs) provide highly flexible platforms to implement sophisticated data processing for scientific space instruments. The dynamic partial reconfiguration (DPR) capability of FPGAs allows it to schedule HW tasks. While this feature adds another dimension of processing power that can be exploited without significantly increasing system complexity and power consumption, there are still several challenges for an efficient DPR use. State-of-the-art concepts concentrate either on resource-efficient implementations at design time or flexible HW task scheduling at runtime. In this paper we propose a balanced algorithm that considers both optimization goals and is well suited for resource-limited space applications
Hardware and Software Task Scheduling for ARM-FPGA Platforms
ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing them in the FPGA fabric. Several computation steps of our case study for a stereo vision application have been accelerated by hardware implementations. Dynamic Partial Reconfiguration places these hardware tasks in the programmable logic at appropriate times. For an efficient scheduling, it needs to be decided when and where to execute a task. Although there already exist hardware/software scheduling strategies and algorithms, none exploit all possible optimization techniques: re-use, prefetching, parallelization, and pipelining of hardware tasks. The scheduling algorithm proposed in this paper takes this into account and optimizes for the objectives latency/throughput and power/energy
FPGA dynamic and partial reconfiguration : a survey of architectures, methods, and applications
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption
Hardware task scheduling for partially reconfigurable FPGAs
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically
extend and adapt the functionality of computing systems, swapping in and out
HW tasks. To coordinate the on-demand task execution, we propose and
implement a run time system manager for scheduling software (SW) tasks on
available processor(s) and hardware (HW) tasks on any number of
reconfigurable regions of a partially reconfigurable FPGA. Fed with the initial
partitioning of the application into tasks, the corresponding task graph, and the
available task mappings, the RTSM considers the runtime status of each task
and region, e.g. busy, idle, scheduled for reconfiguration/execution etc., to
execute tasks. Our RTSM supports task reuse and configuration prefetching to
minimize reconfigurations, task movement among regions to efficiently manage
the FPGA area, and RR reservation for future reconfiguration and execution.
We validate its correctness using our RTSM to execute an image processing
application on a ZedBoard platform. We also evaluate its features within a
simulation framework, and find that despite the technology limitations, our
approach can give promising results in terms of quality of scheduling.Presented on
TUKUTURI: eine dynamisch selbstrekonfigurierbare Softcore Prozessorarchitektur
Der Entwurf von Systemen zur digitalen Signalverarbeitung stellt den Entwickler
vor stetig wachsende Herausforderungen, die durch zunehmende Komplexität von
Anwendungen und die dafür benötigte Steigerung der Leistungsfähigkeit
eingebetteter Systeme verursacht werden. Ein weiterer Aspekt neben der
Leistungsfähigkeit ist die Flexibilität, die es erlaubt, Anwendungen und
Algorithmen auch nach Auslieferung eines Systems zu verändern.
Diese kann zum einen durch Verwendung von FPGAs erreicht werden, die eine
Rekonfiguration der Hardware ermöglichen. Zum anderen können prozessorbasierte
Systeme verwendet werden, die Flexibilität durch Programmierbarkeit
bereitstellen. Anwendungsspezifische Anpassungen der Prozessorarchitektur und
ein hohes Maß an paralleler Datenverarbeitung, beispielsweise durch
VLIW-Prozessoren, stellen dabei Mittel zum Erreichen hoher Leistungen
dar.
Das Thema dieser Arbeit ist die Untersuchung eines Entwurfsprozesses für
anwendungsspezifische Prozessorsysteme. Dieser basiert auf einem flexiblen
SIMD-VLIW-Prozessor, der in großem Umfang konfiguriert und durch zusätzliche
Hardwaremodule erweitert werden kann. Zur Exploration des Entwurfsraums werden
Werkzeuge zur Analyse von Prozessorkonfigurationen in realen Anwendungen
bereitgestellt sowie Methoden zur automatisierten Adaption der Architektur auf
Basis dieser Analyseergebnisse untersucht. Die Kompilierung von Anwendungen für
VLIW-Architekturen wird aufgrund der kombinatorischen Komplexität üblicherweise
mittels statischer Heuristiken durchgeführt, wodurch eine optimale Adaption an
flexible Architekturen erschwert werden kann. Daher werden hier dynamische
Methoden zur Codegenerierung, die auf evolutionären Algorithmen basieren,
untersucht.
Die Umsetzung der Architektur als Softcore auf einem FPGA bietet zusätzlich die
Möglichkeit der dynamischen Adaption der Hardware zur Laufzeit. Diese
Möglichkeiten und deren Einfluss auf die Leistungsfähigkeit der Prozessorsysteme
werden ebenfalls untersucht.
Die Analyse des Entwurfsprozesses in einer exemplarischen Anwendung der
bildbasierten Objekterkennung und der Vergleich mit Implementierungen auf einem
MIPS-Softcore bzw. VLIW-DSP zeigen die Eignung der Methoden zur Adaption von
Softcore-Prozessoren und der EA-basierten Kompilierung von Anwendungen. Die
dynamische Hardwarerekonfiguration zur Laufzeit kann bei reduziertem
Flächenbedarf für die Hardware ohne Leistungsverlust eingesetzt werden
Efficient runtime placement management for high performance and reliability in COTS FPGAs
Designing high-performance, fault-tolerant multisensory electronic systems for
hostile environments such as nuclear plants and outer space within the constraints of
cost, power and flexibility is challenging. Issues such as ionizing radiation, extreme
temperature and ageing can lead to faults in the electronics of these systems. In
addition, the remote nature of these environments demands a level of flexibility and
autonomy in their operations. The standard practice of using specially hardened
electronic devices for such systems is not only very expensive but also has limited
flexibility.
This thesis proposes novel techniques that promote the use of Commercial Off-The-
Shelf (COTS) reconfigurable devices to meet the challenges of high-performance
systems for hostile environments. Reconfigurable hardware such as Field
Programmable Gate Arrays (FPGA) have a unique combination of flexibility and
high performance. The flexibility offered through features such as dynamic partial
reconfiguration (DPR) can be harnessed not only to achieve cost-effective designs as
a smaller area can be used to execute multiple tasks, but also to improve the
reliability of a system as a circuit on one portion of the device can be physically
relocated to another portion in the case of fault occurrence. However, to harness
these potentials for high performance and reliability in a cost-effective manner, novel
runtime management tools are required. Most runtime support tools for
reconfigurable devices are based on ideal models which do not adequately consider
the limitations of realistic FPGAs, in particular modern FPGAs which are
increasingly heterogeneous. Specifically, these tools lack efficient mechanisms for
ensuring a high utilization of FPGA resources, including the FPGA area and the
configuration port and clocking resources, in a reliable manner.
To ensure high utilization of reconfigurable device area, placement management is a
key aspect of these tools. This thesis presents novel techniques for the management
of hardware task placement on COTS reconfigurable devices for high performance
and reliability. To this end, it addresses design-time issues that affect efficient
hardware task placement, with a focus on reliability. It also presents techniques to
maximize the utilization of the FPGA area in runtime, including techniques to
minimize fragmentation. Fragmentation leads to the creation of unusable areas due to
dynamic placement of tasks and the heterogeneity of the resources on the chip.
Moreover, this thesis also presents an efficient task reuse mechanism to improve the
availability of the internal configuration infrastructure of the FPGA for critical
responsibilities like error mitigation. The task reuse scheme, unlike previous
approaches, also improves the utilization of the chip area by offering
defragmentation.
Task relocation, which involves changing the physical location of circuits is a
technique for error mitigation and high performance. Hence, this thesis also provides
a functionality-based relocation mechanism for improving the number of locations to
which tasks can be relocated on heterogeneous FPGAs. As tasks are relocated, clock
networks need to be routed to them. As such, a reliability-aware technique of clock
network routing to tasks after placement is also proposed.
Finally, this thesis offers a prototype implementation and characterization of a
placement management system (PMS) which is an integration of the aforementioned
techniques. The performance of most of the proposed techniques are tested using
data processing tasks of a NASA JPL spectrometer application. The results show that
the proposed techniques have potentials to improve the reliability and performance of
applications in hostile environment compared to state-of-the-art techniques. The task
optimization technique presented leads to better capacity to circumvent permanent
faults on COTS FPGAs compared to state-of-the-art approaches (48.6% more errors
were circumvented for the JPL spectrometer application). The proposed task reuse
scheme leads to approximately 29% saving in the amount of configuration time. This
frees up the internal configuration interface for more error mitigation operations. In
addition, the proposed PMS has a worst-case latency of less than 50% of that of state-of-
the-art runtime placement systems, while maintaining the same level of placement
quality and resource overhead
Dynamic reconfiguration frameworks for high-performance reliable real-time reconfigurable computing
The sheer hardware-based computational performance and programming flexibility
offered by reconfigurable hardware like Field-Programmable Gate Arrays (FPGAs)
make them attractive for computing in applications that require high performance,
availability, reliability, real-time processing, and high efficiency. Fueled by fabrication
process scaling, modern reconfigurable devices come with ever greater quantities of
on-chip resources, allowing a more complex variety of applications to be developed.
Thus, the trend is that technology giants like Microsoft, Amazon, and Baidu now
embrace reconfigurable computing devices likes FPGAs to meet their critical
computing needs. In addition, the capability to autonomously reprogramme these
devices in the field is being exploited for reliability in application domains like
aerospace, defence, military, and nuclear power stations. In such applications, real-time
computing is important and is often a necessity for reliability. As such, applications and
algorithms resident on these devices must be implemented with sufficient
considerations for real-time processing and reliability.
Often, to manage a reconfigurable hardware device as a computing platform for a
multiplicity of homogenous and heterogeneous tasks, reconfigurable operating systems
(ROSes) have been proposed to give a software look to hardware-based computation.
The key requirements of a ROS include partitioning, task scheduling and allocation,
task configuration or loading, and inter-task communication and synchronization.
Existing ROSes have met these requirements to varied extents. However, they are
limited in reliability, especially regarding the flexibility of placing the hardware circuits
of tasks on device’s chip area, the problem arising more from the partitioning
approaches used. Indeed, this problem is deeply rooted in the static nature of the on-chip
inter-communication among tasks, hampering the flexibility of runtime task
relocation for reliability.
This thesis proposes the enabling frameworks for reliable, available, real-time,
efficient, secure, and high-performance reconfigurable computing by providing
techniques and mechanisms for reliable runtime reconfiguration, and dynamic inter-circuit communication and synchronization for circuits on reconfigurable hardware.
This work provides task configuration infrastructures for reliable reconfigurable
computing. Key features, especially reliability-enabling functionalities, which have
been given little or no attention in state-of-the-art are implemented. These features
include internal register read and write for device diagnosis; configuration operation
abort mechanism, and tightly integrated selective-area scanning, which aims to
optimize access to the device’s reconfiguration port for both task loading and error
mitigation.
In addition, this thesis proposes a novel reliability-aware inter-task communication
framework that exploits the availability of dedicated clocking infrastructures in a
typical FPGA to provide inter-task communication and synchronization. The clock
buffers and networks of an FPGA use dedicated routing resources, which are distinct
from the general routing resources. As such, deploying these dedicated resources for
communication sidesteps the restriction of static routes and allows a better relocation
of circuits for reliability purposes.
For evaluation, a case study that uses a NASA/JPL spectrometer data processing
application is employed to demonstrate the improved reliability brought about by the
implemented configuration controller and the reliability-aware dynamic
communication infrastructure. It is observed that up to 74% time saving can be achieved
for selective-area error mitigation when compared to state-of-the-art vendor
implementations. Moreover, an improvement in overall system reliability is observed
when the proposed dynamic communication scheme is deployed in the data processing
application.
Finally, one area of reconfigurable computing that has received insufficient
attention is security. Meanwhile, considering the nature of applications which now turn
to reconfigurable computing for accelerating compute-intensive processes, a high
premium is now placed on security, not only of the device but also of the applications,
from loading to runtime execution. To address security concerns, a novel secure and
efficient task configuration technique for task relocation is also investigated, providing
configuration time savings of up to 32% or 83%, depending on the device; and resource
usage savings in excess of 90% compared to state-of-the-art