4 research outputs found
Flexible, extensible, open-source and affordable FPGA-based traffic generator
International audienceAs high-speed links become ubiquitous in current networks, testing new algorithms at high-speed is essential for researchers. This task often requires traffic to be generated with some specied features : distribution of packet sizes, payload content, number of TCP or UDP ows... When targeting a data rate of many Gb/s, this cannot be done with commodity computers. Commercial traffic generators exist for this task, but they are expensive and do not t the precise needs of researchers. In this paper, we describe an open-source implementation of a traffic generator capable of lling a 10 Gb/s Ethernet link, with traffic features specied in software. The implementation works on a board including an FPGA and a 10 Gb/s network interface, like the Combo from INVEA-TECH or the NetFPGA 10G. These boards are a ordable for research and can provide a congurable and easily extensible traffic generator
Sistema basado en FPGA para la reproducción de tráfico en redes 10 Gigabit Ethernet
El aumento de la penetraciĂłn del uso de Internet, del uso de las redes sociales y
el streaming de video y audio, ha hecho necesario aumentar el ancho de banda
del que disponen los usuarios finales, provocando un incremento considerable del
tráfico tcp/ip que tienen que soportar los primeros niveles de agregación. A la
par que se aumenta el ancho de banda de las redes, es necesario desarrollar e
investigar nuevos sistemas de procesamiento de paquetes que sean capaces de
trabajar a estas tasas de lĂnea.
Generar tráfico que refleje adecuadamente diferentes condiciones y topologĂas de
red, es crĂtico para realizar experimentos válidos sobre testbeds de red, por lo que
la generación de tráfico real es necesaria para poder comprobar el funcionamiento
real de cualquier sistema de procesamiento de paquetes como por ejemplo routers,
rewalls, sistemas IDS, etc. La manera más fiable de generar tráfico real es
mediante la reproducción de tráfico previamente capturado.
El objetivo de este proyecto es el diseño, desarrollo e implementación de una arquitectura
de reproducción de tráfico. Esta arquitectura permitirá retransmitir
tráfico previamente capturado y almacenado en un fichero PCAP. Posibilitará
reproducir dicha captura de tráfico con exactamente el mismo tiempo entre paquetes
con el que fue capturado, asĂ como aplicar distribuciones de tiempos entre
paquetes segĂşn el caso o escenario que se quiera probar.
Para su diseño, se ha planteado una soluciĂłn hĂbrida basada en la plataforma
NetCOPE. Se va a implementar un software de control y un rmware que se
cargará en la FPGA Virtex-5 que proporciona la tarjeta COMBO v2. El software
de control proporcionará al usuario una serie de opciones que le permitirán cargar
un fichero de trazas, cargar unos tiempos entre paquetes y modfi car de manera
interactiva los tiempos entre paquetes cargados.The increasing use of the Internet, social networking and new video and audio
streaming applications, has led to an increment in the end users bandwidth demand.
This has meant a considerable increment in the TCP/IP tra c that the
distribution network has to handle. Due to this increasing bandwidth demand, it
is necessary to develop new packet processing systems that are capable of working
at higher bit rates.
It is critical to perform valid experiments on network testbeds, the use of a tra c
generation tool that adequately re ects di erent network topologies and conditions.
In order to test how the packet processing systems (routers, rewalls, IDS
systems, etc) would operate in a real environment, it is required to generate tra c
as similar as possible to the tra c generated on a real environment. The easiest
way to achieve this is by replicating previously captured real tra c.
The aim of this project is to design, develop and implement a tra c replication
architecture. This architecture will be able to replicate previously captured tra c
stored in a PCAP le. It will allow the replication of the network trace exactly with
the same interpacket times as when it was captured, as well as other interpacket
time distributions depending on the scenario under evaluation.
In this project we propose a hybrid solution based on the NetCOPE platform.
It consist on an administration software and a rmware that will be loaded into
a Virtex-5 FPGA provided by the COMBOv2 network card. The administration
software will provide di erent options to the user. Using these options, the end user
will be able to: load a previously captured pcap le, load the original interpacket
time model and interactively modify the loaded interpackets
Porting NetCOPE Platform to EDK
Tato bakalářská práce se zaobĂrá pĹ™evodem platformy NetCOPE do Xilinx Embedded Development Kit (EDK). HlavnĂm Ăşkolem je vytvoĹ™enĂ anotace hardware platformy NetCOPE pro jejĂ pouĹľitĂ v prostĹ™edĂ EDK. PĹ™ed samotnou implementacĂ anotace je nutnĂ© nastudovat technologii FPGA, platformu NetCOPE a formát PSF pro anotaci IP-core platformy NetCOPE.This bachelor's thesis deals with porting of NetCOPE to Xilinx Embedded Development Kit (EDK). Main task is to create annotation of NetCOPE hardware for using in EDK. Before implementation of annotation itself, it is necessary both to study FPGA technology, possibilities of FPGA progamming, NetCOPE platform and PSF for anotation of NetCOPE’s IP-core.
Application Specific Processor for Stateful Network Traffic Processing
Bakalářská práce se zabĂ˝vá návrhem a implementacĂ aplikaÄŤnÄ› specifickĂ©ho procesoru pro vysokorychlostnĂ stavovĂ© měřenĂ sĂĹĄovĂ˝ch tokĹŻ. HlavnĂm cĂlem je vytvoĹ™enĂ komplexnĂho systĂ©mu pro akceleraci rĹŻznĂ˝ch aplikacĂ z oblasti monitorovánĂ a bezpeÄŤnosti poÄŤĂtaÄŤovĂ˝ch sĂtĂ. AplikaÄŤnÄ› specifickĂ˝ procesor tvořà hardwarovou část systĂ©mu implementovanou v FPGA na akceleraÄŤnĂ sĂĹĄovĂ© kartÄ›. Návrh procesoru je proveden s ohledem na nasazenĂ na sĂtĂch o rychlostech 100 Gb/s a je zaloĹľen na unikátnĂ kombinaci rychlosti hardwarovĂ©ho zpracovánĂ a flexibility softwarovĂ©ho Ĺ™ĂzenĂ vycházejĂcĂ z konceptu softwarovÄ› definovanĂ©ho monitorovánĂ (SDM). VytvoĹ™enĂ˝ systĂ©m prošel funkÄŤnĂ verifikacĂ a v rámci hardwarovĂ©ho testovánĂ byla ověřena jeho reálná propustnost a dalšà vĂ˝konovĂ© parametry.This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.