13,799 research outputs found
InAs nanowire transistors with multiple, independent wrap-gate segments
We report a method for making horizontal wrap-gate nanowire transistors with
up to four independently controllable wrap-gated segments. While the step up to
two independent wrap-gates requires a major change in fabrication methodology,
a key advantage to this new approach, and the horizontal orientation more
generally, is that achieving more than two wrap-gate segments then requires no
extra fabrication steps. This is in contrast to the vertical orientation, where
a significant subset of the fabrication steps needs to be repeated for each
additional gate. We show that cross-talk between adjacent wrap-gate segments is
negligible despite separations less than 200 nm. We also demonstrate the
ability to make multiple wrap-gate transistors on a single nanowire using the
exact same process. The excellent scalability potential of horizontal wrap-gate
nanowire transistors makes them highly favourable for the development of
advanced nanowire devices and possible integration with vertical wrap-gate
nanowire transistors in 3D nanowire network architectures.Comment: 18 pages, 5 figures, In press for Nano Letters (DOI below
p-GaAs nanowire MESFETs with near-thermal limit gating
Difficulties in obtaining high-performance p-type transistors and gate
insulator charge-trapping effects present two major challenges for III-V
complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs
nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates
the need for a gate insulator by exploiting the Schottky barrier at the
metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire
metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical
sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio
, on-resistance ~700 k, contact resistance ~30 k,
peak transconductance 1.2 S/m and high-fidelity ac operation at
frequencies up to 10 kHz. The device consists of a GaAs nanowire with an
undoped core and heavily Be-doped shell. We carefully etch back the nanowire at
the gate locations to obtain Schottky-barrier insulated gates whilst leaving
the doped shell intact at the contacts to obtain low contact resistance. Our
device opens a path to all-GaAs nanowire MESFET complementary circuits with
simplified fabrication and improved performance
A differential memristive synapse circuit for on-line learning in neuromorphic computing systems
Spike-based learning with memristive devices in neuromorphic computing
architectures typically uses learning circuits that require overlapping pulses
from pre- and post-synaptic nodes. This imposes severe constraints on the
length of the pulses transmitted in the network, and on the network's
throughput. Furthermore, most of these circuits do not decouple the currents
flowing through memristive devices from the one stimulating the target neuron.
This can be a problem when using devices with high conductance values, because
of the resulting large currents. In this paper we propose a novel circuit that
decouples the current produced by the memristive device from the one used to
stimulate the post-synaptic neuron, by using a novel differential scheme based
on the Gilbert normalizer circuit. We show how this circuit is useful for
reducing the effect of variability in the memristive devices, and how it is
ideally suited for spike-based learning mechanisms that do not require
overlapping pre- and post-synaptic pulses. We demonstrate the features of the
proposed synapse circuit with SPICE simulations, and validate its learning
properties with high-level behavioral network simulations which use a
stochastic gradient descent learning rule in two classification tasks.Comment: 18 Pages main text, 9 pages of supplementary text, 19 figures.
Patente
Near-thermal limit gating in heavily-doped III-V semiconductor nanowires using polymer electrolytes
Doping is a common route to reducing nanowire transistor on-resistance but
has limits. High doping level gives significant loss in gate performance and
ultimately complete gate failure. We show that electrolyte gating remains
effective even when the Be doping in our GaAs nanowires is so high that
traditional metal-oxide gates fail. In this regime we obtain a combination of
sub-threshold swing and contact resistance that surpasses the best existing
p-type nanowire MOSFETs. Our sub-threshold swing of 75 mV/dec is within 25% of
the room-temperature thermal limit and comparable with n-InP and n-GaAs
nanowire MOSFETs. Our results open a new path to extending the performance and
application of nanowire transistors, and motivate further work on improved
solid electrolytes for nanoscale device applications.Comment: 6 pages, 2 figures, supplementary available at journa
Modelling and simulation of advanced semiconductor devices
This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Greenâs Function formalism
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