Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

Assembling strategies in extrinsic evolvable hardware with bi-directional incremental evolution

Bidirectional incremental evolution (BIE) has been proposed as a technique to overcome the ”stalling” effect in evolvable hardware applications. However preliminary results show perceptible dependence of performance of BIE and quality of evaluated circuit on assembling strategy applied during reverse stage of incremental evolution. The purpose of this paper is to develop assembling strategy that will assist BIE to produce relatively optimal solution with minimal computational effort (e.g. the minimal number of generations)

Generalized disjunction decomposition for the evolution of programmable logic array structures

Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

On evolution of relatively large combinational logic circuits

Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs

A novel genetic algorithm for evolvable hardware

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures

Open-ended evolution to discover analogue circuits for beyond conventional applications

This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s10710-012-9163-8. Copyright @ Springer 2012.Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics

Bidirectional incremental evolution in extrinsic evolvable hardware

Evolvable Hardware (EHW) has been proposed as a new technique to design complex systems. Often, complex systems turn out to be very difficult to evolve. The problem is that a general strategy is too difficult for the evolution process to discover directly. This paper proposes a new approach that performs incremental evolution in two directions: from complex system to sub-systems and from sub-systems back to complex system. In this approach, incremental evolution gradually decomposes a complex problem into some sub-tasks. In a second step, we gradually make the tasks more challenging and general. Our approach automatically discovers the sub-tasks, their sequence as well as circuit layout dimensions. Our method is tested in a digital circuit domain and compared to direct evolution. We show that our bidirectional incremental approach can handle more complex, harder tasks and evolve them more effectively, then direct evolution

Some aspects of an evolvable hardware approach for multiple-valued combinational circuit design

In this paper a gate-level evolvable hardware technique for designing multiple-valued (MV) combinational circuits is proposed for the first time. In comparison with the decomposition techniques used for synthesis of combinational circuits previously employed, this new approach is easily adapted for the different types of MV gates associated with operations corresponding to different algebra types and can include other more complex logical expressions (e.g. singlecontrol MV multiplexer called T-gate). The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. The experimental results show how the success of genetic algorithm depends on the number of columns, the number of rows in circuit structure and levels-back parameter (the number of columns to the left of current cell to which cell input may be connected). We show that the choice of the set of MV gates used radically affects the chances of successful evolution (in terms of number of 100% functional solutions found)

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

Adaptive embedded systems are required in various applications. This work addresses these needs in the area of adaptive image compression in FPGA devices. A simplified version of an evolution strategy is utilized to optimize wavelet filters of a Discrete Wavelet Transform algorithm. We propose an adaptive image compression system in FPGA where optimized memory architecture, parallel processing and optimized task scheduling allow reducing the time of evolution. The proposed solution has been extensively evaluated in terms of the quality of compression as well as the processing time. The proposed architecture reduces the time of evolution by 44% compared to our previous reports while maintaining the quality of compression unchanged with respect to existing implementations. The system is able to find an optimized set of wavelet filters in less than 2 min whenever the input type of data changes

Automatic design of analogue circuits

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits