Performances of Cryptographic Accumulators

International audienceCryptographic accumulators are space/time efficient data structures used to verify if a value belongs to a set. They have found many applications in networking and distributed systems since their in- troduction by Benaloh and de Mare in 1993. Despite this popularity, there is currently no performance evaluation of the different existing de- signs. Symmetric and asymmetric accumulators are used likewise without any particular argument to support either of the design. We aim to es- tablish the speed of each design and their application's domains in terms of their size and the size of the values

Behavior planning for automated highway driving

This work deals with certain components of an automated driving system for highways, focusing on lane change behavior planning. It presents a variety of algorithms of a modular system aiming at safe and comfortable driving. A major contribution of this work is a method for analyzing traffic scenes in a spatio-temporal, curvilinear coordinate system. The results of this analysis are used in a further step to generate lane change trajectories. A total of three approaches with increasing levels of complexity and capabilities are compared. The most advanced approach formulates the problem as a linear-quadratic cooperative game and accounts for the inherently uncertain and multimodal nature of trajectory predictions for surrounding road users. Evaluations on real data show that the developed algorithms can be integrated into current generation automated driving software systems fulfilling runtime constraints

Performances of Cryptographic Accumulators

International audienceCryptographic accumulators are space/time efficient data structures used to verify if a value belongs to a set. They have found many applications in networking and distributed systems since their in- troduction by Benaloh and de Mare in 1993. Despite this popularity, there is currently no performance evaluation of the different existing de- signs. Symmetric and asymmetric accumulators are used likewise without any particular argument to support either of the design. We aim to es- tablish the speed of each design and their application's domains in terms of their size and the size of the values

Predicting Protein Structure Using Parallel Genetic Algorithms

The protein folding problem is a biochemistry Grand Challenge problem. The challenge is to reliably predict natural three-dimensional structures of polypeptides. Genetic algorithms (GAs) are robust, semi-optimal search techniques modeling natural evolutionary processes. Fast messy GAs (fmGAs) are variants of messy GAs that reduce the exponential time complexity to polynomial. This investigation evaluates the merits of parallel SGAs and fmGAs for minimizing the potential energy of a pentapeptide, (Met)-enkephalin. AFIT\u27s energy model is compared to a similar model in a commercial package called QUANTA. Differences between the two models are identified and resolved to enhance GAs\u27 abilities to correctly fold molecules. The steps required to unify the behavior of the two implementations is presented. The effectiveness of SGAs while minimizing the potential energy of (Met)-enkephalin is shown to be highly dependent on the choice of population size and mutation rate. It is also demonstrated that choosing parameters from the Schaffer\u27s proposed guidelines cause SGAs to realize near-optimal performance on this particular application. Parallel SGAs are capable of finding near-optimal conformations of (Met)-enkephalin. Parallel fmGAS should ultimately find better solutions in less time. The experiments performed in this investigation determine limitations of parallel SGAs and fmGAs applied to polypeptide energy minimization

Optimal space communications techniques

Digital multiplication of two waveforms using delta modulation (DM) is discussed. It is shown that while conventional multiplication of two N bit words requires N2 complexity, multiplication using DM requires complexity which increases linearly with N. Bounds on the signal-to-quantization noise ratio (SNR) resulting from this multiplication are determined and compared with the SNR obtained using standard multiplication techniques. The phase locked loop (PLL) system, consisting of a phase detector, voltage controlled oscillator, and a linear loop filter, is discussed in terms of its design and system advantages. Areas requiring further research are identified

Perancangan Dan Pembuatan Perangkat Lunak Deteksi Dan Klasifikasi Citra Dengan Deformable Contour

Kontur Adalah Bentuk Tertentu Dari Sebuah Obyek Berupa Garis Tepi Obyek Tersebut. Melalui Bentuk Kontur Dapat Dijelaskan Ciri Dan Karakter Obyek Yang Bersangkutan. Kontur Dapat Dideteksi Dan Kemudian Diklasifikasikan Dengan Memanfaatkan Nilai Energi Kontur Yang Terdapat Di Dalam Kontur Tersebut Yang Dapat Dihitung Bila Koordinat Kontur Dan Citra Pembentuk Kontur Diketahui. Kemampuan Kontur Untuk Dapat Berubah Bentuk Dimungkinkan Dengan Penggunaan Metode Persamaan Distribusi Medan Acak Markov (Markov Random Field) Yang Dialokasikan Untuk Kontur Tersebut, Perumusan Energi Internal Kontur, Dan Energi Eksternal Yang Merupakan Korelasi Kontur Dengan Citra. Dari Hasil Tersebut Didapatkan Model Kontur Aktif Yang Dikenal Dengan Istilah Generalized Active Contour Model Atau G-Snake. Dalam Tugas Akhir Ini Dibahas Tentang Deteksi Dan Klasifikasi Citra Dengan Memanfaatkan Kontur Yang Dapat Berubah Bentuk. Untuk Proses Deteksi Deformable Contour Digunakan Transformasi Hough Untuk Mereposisikan Kontur Agar Sesuai Dengan Obyek Yang Akan Dideteksi. Sedangkan, Untuk Proses Klasifikasi Digunakan Algoritma Penjumlahan (Summation Algorithm) Yang Akan Dijelaskan Lebih Lanjut Dalam Buku Ini

Near-capacity fixed-rate and rateless channel code constructions

Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers