38,222 research outputs found
Phase Locked Loop Test Methodology
Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications
A short survey on nonlinear models of the classic Costas loop: rigorous derivation and limitations of the classic analysis
Rigorous nonlinear analysis of the physical model of Costas loop --- a
classic phase-locked loop (PLL) based circuit for carrier recovery, is a
challenging task. Thus for its analysis, simplified mathematical models and
numerical simulation are widely used. In this work a short survey on nonlinear
models of the BPSK Costas loop, used for pre-design and post-design analysis,
is presented. Their rigorous derivation and limitations of classic analysis are
discussed. It is shown that the use of simplified mathematical models, and the
application of non rigorous methods of analysis (e.g., simulation and
linearization) may lead to wrong conclusions concerning the performance of the
Costas loop physical model.Comment: Accepted to American Control Conference (ACC) 2015 (Chicago, USA
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Variable domain transformation for linear PAC analysis of mixed-signal systems
This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commercial RF simulators, the circuit’s linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage-domain models, instead of being modeled as strongly-nonlinear systems directly
Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs
This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage
Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System
With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems
Theory of phaselock techniques as applied to aerospace transponders
Phaselock techniques as applied to aerospace transponder
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