Technique of failure analysis for gate oxide defect of Bi-polar CMOS Diffuse (BCD) technology

This research presents failure analysis (FA) works on gate oxide defect of Bi�polar CMOS Diffuse (BCD) technology. The latent problem with electrical degradation in the CMOS performance is due to gate oxide defect. The defect was well known affects the CMOS reliability after certain period of time, temperatures and stress. The FA techniques used for this research were developed using a combination of IDDQ scan test pattern, photo localization by the emission microscope and Field Emission Scanning Electron Microscopy (FE-SEM) for defect inspection. The FA methods successfully evaluated on few failing samples which were taken from customer return with IDDQ failure range from 50µA until less than 1mA. Concurrently, the spotted excessive emission found on the defective samples during photo localization step indicates of gate oxide defect. The defect well observed with FE-SEM analysis on all tested samples after the physical analysis accomplishment until oxide layer. The proposed technique shows an effective method to compensate the existing FA difficulty on gate oxide defect faced by IC manufacturer in micrometer and nanometer scale technology, which having more metal interconnection layers with higher dense. The proposed technique able to construct promising result compared to the conventional techniques which used in the current FA practice due to certain extends of limitation

On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 μm, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm -1 , a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface

Low-temperature process steps for realization of non-volatile memory devices

In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the subsequent functional layers (e.g., gate oxide) can be done using CVD and ALD reactors in a cluster tool. We show that a high nanocrystal density (Si-NC), required for a good functionality of the memory device, can be obtained by using disilane (Si2H6) or trisilane (Si3H8, known as Silcore®) as precursors for LPCVD instead of silane, at a deposition temperature of 325 °C. The nanocrystals are encapsulated with an ALD-Al2O3 layer (deposited at 300 °C), which serves as oxidation barrier. The passivation of the realized structure is done with an ALD-TiN layer deposited at 425 °C. In this work, we realized Al/TiN/Al2O3/Si-NC/SiO2/Si(100) multilayer floating-gate structures, where the crystallized amorphous silicon film was for the time being replaced by a mono-crystalline silicon wafer, and the gate oxide was thermally grown instead of a low-temperature PECVD oxide. The structures were characterized in terms of their performance as memory cells. In addition, the feasibility to use laser crystallization for improving the amorphous silicon films (prior to the gate oxide deposition) was explored

Gate Oxide Reliability and Deuterated CMOS Processing

In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. It appears as if this controversy finds its origin in the different stages (e.g. oxidation or post metal anneal) deuterium is introduced in the CMOS process. This paper investigates this in detail. The obtained results show that the hot carrier degradation only benefits from an isotope effect when deuterium is introduced in the post metal anneal. At the same time, charge to breakdown for high quality oxides does not benefit from an isotope effect, regardless of the processing stage deuterium is introduced, or the gate oxide thickness used. This is verified on two different sets of wafers fabricated in two different laboratories

Shrinking limits of silicon MOSFET's: Numerical study of 10-nm-scale devices

We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, though their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.Comment: 8 pages, 10 figures. Submitted to Special Issue of Superlattices and Microstructures: Third NASA Workshop on Device Modeling, August 199

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved