114,461 research outputs found
The Impact of Deuterated CMOS processing on Gate Oxide Reliability
In recent literature, a controversy has arisen over the question whether deuterium improves the stability of the MOS gate dielectric. In particular, the influence of deuterium incorporation on the bulk oxide quality is not clear. In this letter, deuterium or hydrogen is introduced during either the gate oxidation, postoxidation anneal, and/or the postmetal anneal (PMA). The oxide bulk degradation was evaluated using charge-to-breakdown and stress-induced leakage current; and the oxide interface degradation using hot-carrier degradation and low-frequency noise. The obtained results show that the oxide bulk does not benefit from the presence of deuterium, regardless of the stage of deuterium introduction, or the gate oxide thickness. The oxide interface is more stable only when deuterium is introduced in the PMA
Radiation hardening of MOS devices by boron
A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations
Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region
Simulation of current transients through ultrathin gate oxides during plasma etching
Monte Carlo simulations of electron tunneling through a 3 nm gate oxide during etching of dense patterns of gate electrodes in uniform high-density plasmas reveal two current transients, which occur: (a) when the open area clears, and (b) when the polysilicon lines just become disconnected at the bottom of trenches. The first charging transient is fast (controlled by charging) and may be followed by a steady-state current which lasts until the lines get disconnected. The second charging transient lasts longer; the magnitude of the tunneling current generally decreases as the sloped polysilicon sidewalls become straighter. Most of the damage occurs at the edge gate when the open areas are covered by field oxide; however, the edge gate suffers no damage when the 3 nm oxide extends into the open areas
Design of an Advanced Programmable Current-Source Gate Driver for Dynamic Control of SiC Device
Silicon carbide (SiC) power devices outperform Silicon-based devices in operational voltage levels, power densities, operational temperatures and switching frequencies. However, the gate oxide of SiC-based device is more fragile compared with its Si counterpart. The vulnerability of the gate oxide in SiC power devices requires the development of a gate driver that is able to have more control during the turn-on and turn-off process. This paper proposes an innovative current-source gate driver where the gate current can be fully programmed. The novelty of the gate driver is that the dynamic switching transients and the static on/off-state can be controlled independently. In order to achieve this approach, a signal decomposition and reconstruction technique is proposed to apply the separate control over the dynamic switching transient and the static on/off-state gate voltage respectively. The fundamental principle of the proposed circuit is verified in simulation. In addition, a prototype of the active gate driver has been built and tested to validate the effectiveness of the flexible control over the gate voltage
Technique of failure analysis for gate oxide defect of Bi-polar CMOS Diffuse (BCD) technology
This research presents failure analysis (FA) works on gate oxide defect of Bi�polar CMOS Diffuse (BCD) technology. The latent problem with electrical
degradation in the CMOS performance is due to gate oxide defect. The defect was
well known affects the CMOS reliability after certain period of time, temperatures
and stress. The FA techniques used for this research were developed using a
combination of IDDQ scan test pattern, photo localization by the emission microscope
and Field Emission Scanning Electron Microscopy (FE-SEM) for defect inspection.
The FA methods successfully evaluated on few failing samples which were taken
from customer return with IDDQ failure range from 50µA until less than 1mA.
Concurrently, the spotted excessive emission found on the defective samples during
photo localization step indicates of gate oxide defect. The defect well observed with
FE-SEM analysis on all tested samples after the physical analysis accomplishment
until oxide layer. The proposed technique shows an effective method to compensate
the existing FA difficulty on gate oxide defect faced by IC manufacturer in
micrometer and nanometer scale technology, which having more metal
interconnection layers with higher dense. The proposed technique able to construct
promising result compared to the conventional techniques which used in the current
FA practice due to certain extends of limitation
Palladium gates for reproducible quantum dots in silicon
We replace the established aluminium gates for the formation of quantum dots
in silicon with gates made from palladium. We study the morphology of both
aluminium and palladium gates with transmission electron microscopy. The native
aluminium oxide is found to be formed all around the aluminium gates, which
could lead to the formation of unintentional dots. Therefore, we report on a
novel fabrication route that replaces aluminium and its native oxide by
palladium with atomic-layer-deposition-grown aluminium oxide. Using this
approach, we show the formation of low-disorder gate-defined quantum dots,
which are reproducibly fabricated. Furthermore, palladium enables us to further
shrink the gate design, allowing us to perform electron transport measurements
in the few-electron regime in devices comprising only two gate layers, a major
technological advancement. It remains to be seen, whether the introduction of
palladium gates can improve the excellent results on electron and nuclear spin
qubits defined with an aluminium gate stack
Vertical field-effect transistors in III-V semiconductors
Vertical metal-semiconductor field-effect transistors in GaAs/GaAlAs and vertical metal-oxide-semiconductor field-effect transistors (MOSFET's) in InP/GaInPAs materials have been fabricated. These structures make possible short channel devices with gate lengths defined by epitaxy rather than by submicron photolithography processes. Devices with transconductances as high as 280 mS/mm in GaAs and 60 mS/mm (with 100-nm gate oxide) for the InP/GaInPAs MOSFET's were observed
Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron
Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface
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