A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations

Danchenko, V.

English

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NATIONAL AERONAUTICS AND SPACE ADMINISTRATION
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March 26, 1974 v. DANCHENKO 3,799,813
RADIATION HARDENING OF MOS DEVICES BY BORON
Filed Dec. 9, 1971
I HOUR 10 HOURS 100 HOURS 1000 HOURS
TIME AFTER IRRADIATION
INVENTOR
VITALY DANCHENKO
FIG.
BY
ATTORNEYS
United States Patent Office 3,799,813Patented Mar. 26, 1974
3,799,813
RADIATION HARDENING OF MOS DEVICES
BY BORON
Vitaly Danchenko, Silver Spring, Md., assignor to the
United States of America as represented by the Admin-
istrator of the National Aeronautics and Space Admin-
istration
Filed Dec. 9,1971, Ser. No. 206,266
Int O. H011 7/54
U.S. a. 148—1.5 5 Claims
ABSTRACT OF THE DISCLOSURE
A novel technique is disclosed for radiation hardening
of MOS devices and specifically for stabilizing the gate
threshold potential at room temperature of a radiation
subjected MOS field-effect device of the type having a semi-
conductor substrate, an insulating layer of oxide on the
substrate, and a gate electrode disposed on the insulating
layer. In the preferred embodiment, the novel inventive
technique contemplates the introduction of boron into the
insulating oxide, the boron being introduced within a
layer of the oxide of about 100 A-300 A thickness im-
mediately adjacent the semiconductor-insulator interface.
The concentration of boron in the oxide layer is preferably
maintained on the order of 1018 atoms/cm.3. The novel
technique serves to reduce and substantially annihilate
radiation induced positive gate charge accumulations,
which accumulations, if not eliminated, would cause shift-
ing of the gate threshold potential of a radiation subjected
MOS device, and thus render the device unstable and/or
inoperative.
ORIGIN OF THE INVENTION
The invention described herein was made by an em-
ployee of the United States Government and may be
manufactured and used by or for the government for gov-
ernmental purposes without the payment of any royalties
thereon or therefor.
BACKGROUND OF THE INVENTION
This invention generally relates to MOS devices and
particularly concerns a technique whereby the gate thresh-
old potential, generally at room temperature, of a radia-
tion subjected MOS field-effect device is stabilized.
A MOS (metal-oxide-semiconductor) device, as is
known, includes a semiconductor substrate, an insulating
layer of oxide on the substrate, and a gate electrode dis-
posed on the insulating layer. With a MOS field-effect
transistor, for example, additional source and drain elec-
trodes are disposed to either side of the gate electrode
and a lateral current may be caused to flow between the
source and drain electrodes through application of proper
bias potential to the gate electrode. Specifically, and in the
so-called "enhancement" mode, application of a biased po-
tential to the gate produces a conducting layer beneath
the metal oxide allowing lateral current flow between the
source and drain electrodes. In a second mode of opera-
tion such as the so-called "depletion" mode, application
of a bias potential to the gate electrodes produces an in-
sulating region between the source and drain electrodes
which serves to decrease current conduction.
With the usual MOS devices, several volts, such as three
or four volts of negative potential is necessary to be ap-
plied to the gate in the p-channel enhancement mode of
the MOS device whereas, with a n-channel device, a few
volts of positive potential applied to the gate is needed. By
way of definition, the gate voltage at which approximately
ten microamperes of drain current flows is commonly de-
fined as the gate threshold potential of any particular
MOS device.
Such MOS devices, when subjected or exposed to ion-
izing radiation such as would occur in a space environ-
ment, suffer radiation damage in the form of charge
trapped in the oxide and/or at the oxide-semiconductor
5 interface and undergo various changes in the electrical
characteristics thereof. Such damage is not always per-
manent, but can oftentimes be "healed" or reduced
through a time and/or temperature annealing process.
One particular dominant and harmful effect on MOS
jO devices due to their exposure to radiation has been a shift
in the above-described gate threshold potential, these shifts
commonly occurring toward the more negative gate volt-
ages. As a result of these shifts in the gate threshold po-
tentials, and at sufficient enough doses of ionizing radia-
15 tion, the devices and the circuits in which they are placed
become unstable and in some instances are actually ren-
• dered inoperative.
In order to safeguard the operation of electronic cir-
cuits which contain MOS devices such as on board a
20 spacecraft, for example, the MOS devices are normally
shielded against the space ionizing radiation, the shielding
normally comprising a heavy material designed to absorb
most of the ionizing radiation from space and also radia-
tion emanating from any other sources that might be
25 present on board the spacecraft itself, such as a nuclear
power source or the like. As can be appreciated, however,
the utilization of such shielding materials greatly in-
creases the weight of a spacecraft and, as such, may pose
severe disadvantages particularly for deep space missions
30 where weight limitations are severe. Furthermore, even
if the radiation shielding is sufficient, the danger always
exists that the shielding itself might be improperly de-
signed or that an unexpected source of radiation may ap-
pear, or that the probability of malfuction of the various
35 circuits may increase due to even small changes in the
operating characteristics of the MOS devices.
SUMMARY OF THE INVENTION
^O It is a primary object of the instant invention to pro-
vide a novel technique whereby MOS devices of the type
described can be "hardened" against radiation without re-
quiring the utilization of external shielding.
A more specific object of the instant invention concerns
45 the provision of a radiation hardening technique for MOS
devices whereby the gate threshold potential, at room tem-
perature, of a radiation subjected MOS field-effect device
is stabilized against radiation-induced shifting thereof.
These important objects, as well as others which will
50 become apparent as the description proceeds, are imple-
mented by the instant invention which broadly can be
described as comprising a novel technique for radiation
hardening of MOS devices and specifically for stabilizing
the gate threshold potential at room temperature of a
55 radiation subjected MOS field-effect device of the type
having a semiconductor substrate, and a gate electrode
disposed on the insulating layer.
In the preferred embodiment, the novel inventive tech-
nique contemplates the introduction of boron or other
60 elements having so-called "acceptor" properties into the
insulating oxide, the boron being introduced with a layer
of the oxide of about 100 A-300 A. thickness immediately
adjacent the semiconductor-insulator interface. The con-
centration of boron in the oxide layer is preferably main-
65 tained on the order of 1018 atoms/cm.3. The novel tech-
nique serves to reduce and substantially annihilate radia-
tion induced positive gate charge accumulations, which ac-
cumulations, if not eliminated, would cause shifting of
the gate threshold potential of a radiation subjected MOS
70 device, and thus render the device as well as the asso-
ciated circuitry unstable and/or inoperative.
3,799,813
BRIEF DESCRIPTION OF THE DRAWINGS
The invention itself will be better understood and fur-
ther features thereof will be recognized from the follow-
ing detailed description of a preferred inventive embodi-
ment, such description referring to the appended sheet of
drawings, wherein:
FIG. 1 is a side elevational section, partially broken
away for illustrative clarity, of a typical MOS field-effect
device subjected to a source of external ionizing radiation;
and
FIG. 2 is a graphical illustration of the shifting of gate
threshold potential of an MOS device subjected to radia-
tion, and the time for self-recovery of such radiation
damage at room temperature.
DETAILED DESCRIPTION OF A PREERRED
INVENTIVE EMBODIMENT
Referring now to FIG. 1 of the appended drawings, a
typical MOS field-effect device is illustrated such as would
be utilized in large scale integrated logic and memory
circuits, for example. Such device typically comprises a
substrate 10 of semiconductor material such as silicon,
an insulating layer 12 of oxide such as silicon oxide
(SiO2) disposed on the semiconductor substrate 10 and
a metallic gate electrode 14 disposed on the insulating
layer 12, to which gate electrode 14 a connecting wire
16 may be attached. Source and drain regions 18 and 20,
respectively, are provided in the semiconductor sub-
strate 10 and have associated therewith metallic elec-
trodes 22 and 24, respectively, along with connecting wires
26 and 28.
As briefly explained at the outset, such MOS field-effect
devices are composed of either n-channel or p-channel
types or, in a complementary version, of both n-channel
and p-channel types. With a p-channel MOS device, the
-semiconductor substrate 10 would be fabricated of n-
type silicon, for example, and the source and drain
regions 18 and 20, respectively, would incorporate p-type
the appended drawings. In FIG. 2, the abscissa of the
curve represents deviations in gate threshold potential
from a normal or "zero" value of an MOS device when
subjected to external radiation, and the ordinate of the
5 curve represents the self-recovery or healing time in hours
of the gate threshold potential, i.e., the time necessary, at
room temperature, for the radiation damage to the MOS
device to be cured at room temperature.
For a typical p-channel MOS device, curve 36
10 represents the rate of recovery, whereas for a typical
n-channel MOS device, dotted-line curve 38 represents the
recovery rate. These relatively slow healing times as can
be appreciated from a review of the graphs renders the
typical MOS device unsuitable for operation in an ex-
15 ternal radiation environment unless physical shielding is
utilized.
Applicant has discovered, however, that the introduc-
tion of boron or other elements have so-called "acceptor"
properties into the insulating oxide layer 12 at the semi-
20 conductor-insulator interface 34 of the device depicted
in FIG. 1, for example, reduces the radiation induced
positive gate charge accumulations 32. Specifically, the
novel technique of the instant invention contemplates the
introduction of boron into a thin layer of about 100 A.-
25 300 A. of the gate oxide 12 immediately at the semi-
conductor-insulator interface 34 so as to effect the annihi-
lation or leak off of the radiation-induced accumulated
positive charges. In the preferred inventive embodiment,
the concentration of boron in the oxide layer is main-
30 tained on the order of 1018 atoms/cm.3.
By so introducing boron in the above-described man-
ner, a rapid self-recovery of the threshold potential in
radiation exposed or subjected n- and p-channel MOS
devices at room temperature will result and, in this
35 picted in FIG. 2 is on the order of 1018 atoms/cm.3. The
appended drawings. Curve 40 is illustrative of the self-
recovery time, at room temperature, of the gate threshold
potential of a p-type MOS field-effect device, whereas
silicon achieved through suitable doping of the underlying ,n dotted-line curve 42 represents the self-recovery time of
„_!__,. *_ T-IJ^I- __ _ _i i *rr^ci .e_tj -**-_* j • *i__ ^u an n-cnannelsubstrate. With an n-channel MOS field-effect device, the
underlying semiconductor substrate 10 would be com-
posed of p-type silicon and the source and drain regions
18 and 20, respectively, would comprise n-type silicon,
for example. As mentioned, current flow between the
source and drain regions 18 and 20 of the MOS device is
controlled by a voltage applied to the gate electrode 14
and thus to the insulating oxide layer 12. Specifically,
to turn on a p-channel enhancement mode MOS device a
few volts, such as 3 or 4 volts of negative potential is
necessary and to turn on a n-channel MOS device, a few
volts of positive potential applied to the gate is needed.
The threshold potential of a given MOS field-effect device
is defined herein as being the gate voltage at which ap-
proximately 10 microamperes of drain current is caused
to flow.
When an MOS field-effect device of the type described
with respect to FIG. 1 is subjected or exposed to an ex-
ternal source of ionizing radiation such as generally de-
picted by reference numeral 30, ionization of the gate in-
sulating oxide 12 occurs due to the energetic particles of
the external radiation 30 such as is present in the space
environment. A subsequent accumulation of positive
charges such as indicated by reference numeral 32 will
build up in the oxide layer 12 generally adjacent the semi-
conductor-insulator interface 34, The specific region of
the oxide layer 12 in which most of the radiation-
induced positive charges accumulate has been found to
be within about 100 A. of the semiconductor-insulator
interface 34. This positive radiation-induced charge ac-
cumulation in the gate oxide 12 comprises the cause of 70
the mentioned shifts in the threshold potentials of MOS
devices subjected or exposed to external radiation.
This radiation damage in the form of shifts in gate
threshold potential is, to some extent, self-healing at room
MOS device at room temperature, such
devices being treated in accordance with the radiation
hardening technique of the instant invention. As can be
appreciated from this illustrative graphical data, a com-
plete recovery after irradiation with an external radiation
45 dose of approximately 1013 eleclrons/cm.2 at 1.5 me./v.
of the threshold potentials of n-channel MOS devices has
been achieved in accordance with the instant invention in
somewhat less than 8 hours at room temperature, and, in
p-channel MOS devices treated in accordance with the
50 technique of the instant invention, recovery has oc-
curred in less than 3 hours after irradiation as depicted
by curve 40 in FIG. 2, whereas no recovery would occur
- in the -untreated MOS devices as depicted by curve 36
of FIG. 2. As should be appreciated, with the novel radi-
ation hardening technique described herein, it now is
possible to construct n-channel, p-channel, and comple-
mentary MOS integrated circuits which will substantially
be immune to space radiation as far as the shift in the
gate threshold potentials are concerned. In fact, it should
be recognized that in space, radiation is of an even lower
dose rate than that contemplated above even in the more
highly concentrated regions of the Van Allen belts, so
that the self-recovery of MOS field-effect devices treated
in accordance with the instant invention would be much
faster than would be the accumulation of positive charges
in the oxide layer.
As explained, the preferred concentration of boron in
the gate oxide layer of an MOS device which produced
the rapid self-recovery of the threshold potential as de-
picted in FIG. 2 is on the order of 1418 atoms/cm.3. The
smaller the boron concentration, the slower is the re-
covery of the threshold potentials. For purposes of ex-
planation, it should be understood that an estimated
boron impurity concentration in the typical devices that
55
60
65
temperature and attention is herein directed to FIG. 2 of 75 exhibit a slow recovery at room temperature such as the
3,799,813
n-channel sample depicted by curve 38, is only about
2x10" atoms/cm.3.
The specific mechanisms by which the introduction of
boron in the above-described fashion serves to reduce
and substantially annihilate radiation-induced positive
gate charge accumulations in the oxide of an MOS device
is not entirely understood though it can be theorized that
the positive induced charges are either diffused into the
semiconductor region, or contained with traps of nega-
tive charge states such as boron atoms in silicon. In any
event, the annihilation of such charges have been ex-
perimentally observed rendering the boron treated MOS
device essentially self-healing and effecting spontaneous
recovery of radiation damage at room temperature,
which temperature is herein commonly defined as 25° C.
A number of methods or techniques typical to those
known in the prior art can be utilized to introduce boron
into the gate oxide of the MOS device. One method for
example, comprises the usual gaseous tribromide method
wherein, after boron diffusion at from 700-1200° C. into
300 A. of thermally grown oxide, the remainder of the
gate oxide, up to 1100 A. thick may be built up by
pyrolytic deposition. Other methods of boron introduction
are diffusion of boron from a boron nitrite wafer and the
6
5
10
15
type having a semiconductor substrate, an insulating layer
of oxide on the substrate, and a gate electrode disposed
on the insulating layer, said method comprising the step
of introducing boron into the insulating oxide layer at the
semiconductor-insulator interface so as to reduce radia-
tion induced positive gate charge accumulations.
2. The method defined in claim 1, in which the boron
is introduced within a layer of the oxide of about 100 A.-
300 A. thickness immediately adjacent the semiconductor-
insulator interface.
3. The method defined in claim 2, in which the con-
centration of boron in the oxide layer is maintained on
the order of 1018 atoms/cm.3.
4. The method defined in claim 2, wherein said boron
is introduced into the oxide layer by diffusion.
5. The method defined in claim 2, wherein said boron
is introduced into the oxide layer by ion implantation.
References Cited
20 UNITED STATES PATENTS
3,442,721 5/1969 McCaldin et al 148—1.5 X
3,448,353 6/1969 Gallagher et al. 317—235
3,733,222 5/1973 Schiller 148—1.5
ion implantation method, as is known. __
 T T-»T?vi7 A VXTT? UTT-T-T T~T->/~T- T. • *• •It should now be apparent that the objects initially set 25 L' DEWAYNE RUTLEDGE, Primary Examiner
forth at the outset of this specification have successfully J. M. DAVIS, Assistant Examiner
been achieved. v
What is claimed is: U.S. Cl. X.R.
1. A method of stabilizing the gate threshold potential „«
of a radiation subjected MOS field-effect device of the
148—186; 317—235


Radiation hardening of MOS devices by boron

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