Design Space Exploration and Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays: Device-Circuit Non-Idealities and System Accuracy

In-memory computing (IMC) utilizing synaptic crossbar arrays is promising for deep neural networks to attain high energy efficiency and integration density. Towards that end, various CMOS and post-CMOS technologies have been explored as promising synaptic device candidates which include SRAM, ReRAM, FeFET, SOT-MRAM, etc. However, each of these technologies has its own pros and cons, which need to be comparatively evaluated in the context of synaptic array designs. For a fair comparison, such an analysis must carefully optimize each technology, specifically for synaptic crossbar design accounting for device and circuit non-idealities in crossbar arrays such as variations, wire resistance, driver/sink resistance, etc. In this work, we perform a comprehensive design space exploration and comparative evaluation of different technologies at 7nm technology node for synaptic crossbar arrays, in the context of IMC robustness and system accuracy. Firstly, we integrate different technologies into a cross-layer simulation flow based on physics-based models of synaptic devices and interconnects. Secondly, we optimize both technology-agnostic design knobs such as input encoding and ON-resistance as well as technology-specific design parameters including ferroelectric thickness in FeFET and MgO thickness in SOT-MRAM. Our optimization methodology accounts for the implications of device- and circuit-level non-idealities on the system-level accuracy for each technology. Finally, based on the optimized designs, we obtain inference results for ResNet-20 on CIFAR-10 dataset and show that FeFET-based crossbar arrays achieve the highest accuracy due to their compactness, low leakage and high ON/OFF current ratio

Digital implementation of a wavelet-based event detector for cardiac pacemakers

This paper presents a digital hardware implementation of a novel wavelet-based event detector suitable for the next generation of cardiac pacemakers. Significant power savings are achieved by introducing a second operation mode that shuts down 2/3 of the hardware for long time periods when the pacemaker patient is not exposed to noise, while not degrading performance. Due to a 0.13-mu m CMOS technology and the low clock frequency of 1 kHz, leakage power becomes the dominating power source. By introducing sleep transistors in the power-supply rails, leakage power of the hardware being shut off is reduced by 97%. Power estimation on RTL-level shows that the overall power consumption is reduced by 67% with a dual operation mode. Under these conditions, the detector is expected to operate in the sub-mu W region. Detection performance is evaluated by means of databases containing electrograms to which five types of exogenic and endogenic interferences are added. The results show that reliable detection is obtained at moderate and low signal to noise-ratios (SNRs). Average detection performance in terms of detected events and false alarms for 25-dB SNR is P-D = 0.98 and P-FA = 0.014, respectively

Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology. In my thesis, An introduction to domino logic, The impact of CMOS technology scaling on the performance of domino CMOS logic, Three Phase Domino Logic Circuit, High-performance noise-tolerant circuit techniques for CMOS dynamic logic and other Domino logic techniques are studied and corresponding Domino logic techniques have been designed and simulated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in sub threshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper. To assure high performance in noise tolerant techniques, the inevitable effects like leakage currents and charge distribution have to be minimized. In this thesis few modifications have also been made to already existing domino techniques and different Domino logic circuits are simulated in both Cadence virtuoso (implemented using GPDK090- library of 90nm technology) and Mentor graphics (implemented at different technologies like Tsmc 035.mod, Tsmc 025.mod, Tsmc 018.mod) environments. The performance parameters are also compared with other standard architectures of Domino logic

Impacts of Cmos Scaling on the Analog Design

The advancement of the CMOS fabrication process has pushed the CMOS transistor scaling to the sub-100nm node. While process fabrication and logic designers advocated CMOS scaling consistent with Moore's Law, circuit engineers are struggling with the high leakage current, low power supply, and high power consumption. For the analog circuit designer, things become even worse due to the loss in dynamic range.The objective of this research was to investigate the impacts of the CMOS scaling on the analog design and proposed analog scaling rule: the overdrive voltage should scale at the same rate or faster than the supply voltage to maintain a power settling product efficiency which is constant or improving. To avoid a power consumption penalty, the final specifications for the analog power supply will stall at a voltage of near 1.1V, with an overdrive voltage of 0.1V. Device thresholds must be limited to an approximate voltage 0.3V for analog designs. Due to the reducing self-gain of the transistor from the scaling, multistage OTA topologies should be adopted to achieve high gain and high bandwidth. Different OTA topologies were analyzed in close loop form and compared based on a power settling product efficiency criteria. The nested gain boosted cascode OTA topology was found to have the best efficiency under high supply voltage, high overdrive voltage or low supply voltage, low overdrive voltage. Finally, a 2V 20Msample/s 11-bit pipelined ADC was designed as an example to demonstrate the benefits of the nested cascode OTA application to low voltage pipelined ADC design. The size of the ADC stages was optimally scaled to achieve low power consumption. The full ADC was simulated on the behavior model level by using Matlab Simulink. Cadence simulations and the Peregrine 0.5um SOS device models were used to verify critical components of the ADC further demonstrating feasibility.Electrical Engineering Technolog

Variability-aware low-power techniques for nanoscale mixed-signal circuits.

New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored

Power supply noise in delay testing

As technology scales into the Deep Sub-Micron (DSM) regime, circuit designs have become more and more sensitive to power supply noise. Excessive noise can significantly affect the timing performance of DSM designs and cause non-trivial additional delay. In delay test generation, test compaction and test fill techniques can produce excessive power supply noise. This will eventually result in delay test overkill. To reduce this overkill, we propose a low-cost pattern-dependent approach to analyze noise-induced delay variation for each delay test pattern applied to the design. Two noise models have been proposed to address array bond and wire bond power supply networks, and they are experimentally validated and compared. Delay model is then applied to calculate path delay under noise. This analysis approach can be integrated into static test compaction or test fill tools to control supply noise level of delay tests. We also propose an algorithm to predict transition count of a circuit, which can be applied to control switching activity during dynamic compaction. Experiments have been performed on ISCAS89 benchmark circuits. Results show that compacted delay test patterns generated by our compaction tool can meet a moderate noise or delay constraint with only a small increase in compacted test set size. Take the benchmark circuit s38417 for example: a 10% delay increase constraint only results in 1.6% increase in compacted test set size in our experiments. In addition, different test fill techniques have a significant impact on path delay. In our work, a test fill tool with supply noise analysis has been developed to compare several test fill techniques, and results show that the test fill strategy significant affect switching activity, power supply noise and delay. For instance, patterns with minimum transition fill produce less noise-induced delay than random fill. Silicon results also show that test patterns filled in different ways can cause as much as 14% delay variation on target paths. In conclusion, we must take noise into consideration when delay test patterns are generated

Mise en oeuvre de l'aspect démonstrateur des transistors mono-électroniques

Depuis 1965, la loi de Moore, loi de doublement du nombre de transistors dans une puce tous les deux ans, n’a jamais été contredite. II faut attendre septembre 2007 pour que son inventeur lui-même, Gordon Moore, ne la considère plus valide et estime sa fin dans les dix à quinze ans à venir. Le problème des limites physiques de la technologie CMOS actuelle est alors aujourd’hui posé : jusqu’où la miniaturisation peut-elle continuer? Combien d'atomes faut-il pour faire un transistor fonctionnel ? Y a-t-il d'autres matériaux que les semiconducteurs qui permettraient d'aller au delà des limites physiques, ou encore d'autres moyens de coder l'information de façon plus efficace? La technologie des transistors à un électron (SET, Single Electron Transistor) est une des solutions possible et semble très prometteuse. Bien souvent cantonné à un fonctionnement bien en dessous de la température ambiante, les premiers SETs métalliques démontrant un caractère typique de blocage de Coulomb à des températures dépassant 130 °C sont une des premières réussites du projet "SEDIMOS" ici à l'Université de Sherbrooke. Véritable couteau-suisse, le SET présente des caractéristiques électriques qui vont au delà de la technologie CMOS actuelle tout en pouvant copier cette dernière sans grande difficulté. Dans un circuit, il faut cependant lui adressé [i.e. adresser] certains problèmes tel [i.e. tels] qu’un faible courant de commande, un faible gain en tension et un délai important. Mais tous ces aléas peuvent être cependant contournés ou réduits par une conception adaptée de ces circuits. Cependant, il existe une difficulté à fabriquer de multiples SETs ayant des caractéristiques électriques similaires. En outre, les circuits peuvent exiger des SETs avec un haut niveau de performance. Souhaitant repousser les limites actuelles de la logique SET, le but de cette maîtrise est de réaliser un inverseur SET développant principalement les deux caractéristiques critiques mentionnées dans le paragraphe précédent. Sous un travail à température ambiante, voir supérieur, l'inverseur devra développer un gain en tension supérieur à l'unité. Les SET métalliques présentés dans ce travail sont fabriqués sur un substrat de silicium oxydé par oxydation sèche. Le procédé de fabrication utilisé est cependant compatible avec l'unité de fabrication finale du CMOS, Back End of Line (BEOL). Un coût réduit, un faible bilan thermique, et une amélioration de la densité d'intégration dans le cadre d'une production de masse de circuits hautement intégrés rendent ce procédé de fabrication très attrayant. L'objectif principal de cette maîtrise peut être divisé en 3 parties : (1) L'étude des paramètres électriques tels que les tension, gain, capacité d'attaque et puissance du circuit inverseur SET, (2) l'amélioration des performances de la logique SET grâce à la modification des paramètres physiques des SETs et de l'architecture de leurs circuits et (3) la présentation des résultats de mesures électriques