Applications of Finite Model Theory: Optimisation Problems, Hybrid Modal Logics and Games.

There exists an interesting relationships between two seemingly distinct fields: logic from the field of Model Theory, which deals with the truth of statements about discrete structures; and Computational Complexity, which deals with the classification of problems by how much of a particular computer resource is required in order to compute a solution. This relationship is known as Descriptive Complexity and it is the primary application of the tools from Model Theory when they are restricted to the finite; this restriction is commonly called Finite Model Theory. In this thesis, we investigate the extension of the results of Descriptive Complexity from classes of decision problems to classes of optimisation problems. When dealing with decision problems the natural mapping from true and false in logic to yes and no instances of a problem is used but when dealing with optimisation problems, other features of a logic need to be used. We investigate what these features are and provide results in the form of logical frameworks that can be used for describing optimisation problems in particular classes, building on the existing research into this area. Another application of Finite Model Theory that this thesis investigates is the relative expressiveness of various fragments of an extension of modal logic called hybrid modal logic. This is achieved through taking the Ehrenfeucht-Fraïssé game from Model Theory and modifying it so that it can be applied to hybrid modal logic. Then, by developing winning strategies for the players in the game, results are obtained that show strict hierarchies of expressiveness for fragments of hybrid modal logic that are generated by varying the quantifier depth and the number of proposition and nominal symbols available

Field effect transistor and method of construction thereof

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration

Construction of controlled-NOT gate based on microwave-activated phase (MAP) gate in two transmon system

We experimentally constructed an all-microwave scheme for the controlled-NOT (cNOT) gate between two superconducting transmon qubits in a three dimensional cavity. Our cNOT gate is based on the microwave-activated phase (MAP) gate, which requires an additional procedure to compensate the accumulated phases during the operation of the MAP gate. We applied Z-axis phase gates using microwave hyperbolic secant pulse on both qubits with adequate rotation angles systematically calibrated by separate measurements.We evaluated the gate performance of the constructed cNOT gate by performing two-qubit quantum process tomography (QPT). Finally, we present the experimental implementation of Deutsch-Jozsa algorithm using the cNOT gate

50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT syste

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region

Programmable quantum gate arrays

We show how to construct quantum gate arrays that can be programmed to perform different unitary operations on a data register, depending on the input to some program register. It is shown that a universal quantum gate array - a gate array which can be programmed to perform any unitary operation - exists only if one allows the gate array to operate in a probabilistic fashion. The universal quantum gate array we construct requires an exponentially smaller number of gates than a classical universal gate array.Comment: 3 pages, REVTEX. Submitted to Phys. Rev. Let

Gate errors in solid state quantum computer architectures

We theoretically consider possible errors in solid state quantum computation due to the interplay of the complex solid state environment and gate imperfections. In particular, we study two examples of gate operations in the opposite ends of the gate speed spectrum, an adiabatic gate operation in electron-spin-based quantum dot quantum computation and a sudden gate operation in Cooper pair box superconducting quantum computation. We evaluate quantitatively the non-adiabatic operation of a two-qubit gate in a two-electron double quantum dot. We also analyze the non-sudden pulse gate in a Cooper-pair-box-based quantum computer model. In both cases our numerical results show strong influences of the higher excited states of the system on the gate operation, clearly demonstrating the importance of a detailed understanding of the relevant Hilbert space structure on the quantum computer operations.Comment: 6 pages, 2 figure

Design of an Advanced Programmable Current-Source Gate Driver for Dynamic Control of SiC Device

Silicon carbide (SiC) power devices outperform Silicon-based devices in operational voltage levels, power densities, operational temperatures and switching frequencies. However, the gate oxide of SiC-based device is more fragile compared with its Si counterpart. The vulnerability of the gate oxide in SiC power devices requires the development of a gate driver that is able to have more control during the turn-on and turn-off process. This paper proposes an innovative current-source gate driver where the gate current can be fully programmed. The novelty of the gate driver is that the dynamic switching transients and the static on/off-state can be controlled independently. In order to achieve this approach, a signal decomposition and reconstruction technique is proposed to apply the separate control over the dynamic switching transient and the static on/off-state gate voltage respectively. The fundamental principle of the proposed circuit is verified in simulation. In addition, a prototype of the active gate driver has been built and tested to validate the effectiveness of the flexible control over the gate voltage